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@@ -7,7 +7,6 @@
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*/
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#ifndef ARMV7_H
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#define ARMV7_H
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-#include <linux/types.h>
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/* Cortex-A9 revisions */
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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@@ -41,6 +40,9 @@
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
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#define ARMV7_CLIDR_CTYPE_UNIFIED 4
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+#ifndef __ASSEMBLY__
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+#include <linux/types.h>
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+
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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@@ -58,4 +60,6 @@ void v7_outer_cache_inval_all(void);
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void v7_outer_cache_flush_range(u32 start, u32 end);
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void v7_outer_cache_inval_range(u32 start, u32 end);
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+#endif /* ! __ASSEMBLY__ */
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+
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#endif
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