arm: lpc32xx: mux: add missing registers

Add missing registers in struct definition.
Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011).

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>

arch/arm/include/asm/arch-lpc32xx/cpu.h

@@ -27,7 +27,7 @@
 #define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
 #define RTC_BASE	0x40024000	/* RTC registers base               */
 #define GPIO_BASE	0x40028000	/* GPIO registers base              */
-#define MUX_BASE	0x40028100	/* MUX registers base               */
+#define MUX_BASE	0x40028000	/* MUX registers base               */
 #define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
 #define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
 #define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */

arch/arm/include/asm/arch-lpc32xx/mux.h

@@ -12,7 +12,24 @@
  */
 
 struct mux_regs {
+	u32 reserved1[10];
+	u32 p2_mux_set;
+	u32 p2_mux_clr;
+	u32 p2_mux_state;
+	u32 reserved2[51];
 	u32 p_mux_set;
 	u32 p_mux_clr;
 	u32 p_mux_state;
+	u32 reserved3;
+	u32 p3_mux_set;
+	u32 p3_mux_clr;
+	u32 p3_mux_state;
+	u32 reserved4;
+	u32 p0_mux_set;
+	u32 p0_mux_clr;
+	u32 p0_mux_state;
+	u32 reserved5;
+	u32 p1_mux_set;
+	u32 p1_mux_clr;
+	u32 p1_mux_state;
 };