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@@ -15,6 +15,8 @@
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#include <i2c.h>
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#include <i2c.h>
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#include <linux/errno.h>
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#include <linux/errno.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clk.h>
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+#include <dm.h>
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+#include <mapmem.h>
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/*
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/*
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* Provide default speed and slave if target did not
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* Provide default speed and slave if target did not
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@@ -47,6 +49,14 @@ struct lpc32xx_i2c_base {
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u32 stxfl;
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u32 stxfl;
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};
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};
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+#ifdef CONFIG_DM_I2C
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+struct lpc32xx_i2c_dev {
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+ struct lpc32xx_i2c_base *base;
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+ int index;
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+ uint speed;
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+};
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+#endif /* CONFIG_DM_I2C */
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+
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/* TX register fields */
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/* TX register fields */
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#define LPC32XX_I2C_TX_START 0x00000100
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#define LPC32XX_I2C_TX_START 0x00000100
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#define LPC32XX_I2C_TX_STOP 0x00000200
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#define LPC32XX_I2C_TX_STOP 0x00000200
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@@ -61,11 +71,13 @@ struct lpc32xx_i2c_base {
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#define LPC32XX_I2C_STAT_NAI 0x00000004
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#define LPC32XX_I2C_STAT_NAI 0x00000004
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#define LPC32XX_I2C_STAT_TDI 0x00000001
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#define LPC32XX_I2C_STAT_TDI 0x00000001
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+#ifndef CONFIG_DM_I2C
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static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
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static struct lpc32xx_i2c_base *lpc32xx_i2c[] = {
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(struct lpc32xx_i2c_base *)I2C1_BASE,
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(struct lpc32xx_i2c_base *)I2C1_BASE,
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(struct lpc32xx_i2c_base *)I2C2_BASE,
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(struct lpc32xx_i2c_base *)I2C2_BASE,
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(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
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(struct lpc32xx_i2c_base *)(USB_BASE + 0x300)
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};
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};
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+#endif
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/* Set I2C bus speed */
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/* Set I2C bus speed */
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static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
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static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base,
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@@ -241,6 +253,7 @@ static int __i2c_write(struct lpc32xx_i2c_base *base, u8 dev, uint addr,
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return 0;
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return 0;
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}
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}
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+#ifndef CONFIG_DM_I2C
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static void lpc32xx_i2c_init(struct i2c_adapter *adap,
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static void lpc32xx_i2c_init(struct i2c_adapter *adap,
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int requested_speed, int slaveadd)
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int requested_speed, int slaveadd)
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{
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{
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@@ -294,3 +307,80 @@ U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, lpc32xx_i2c_init, NULL,
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100000,
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100000,
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0,
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0,
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2)
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2)
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+#else /* CONFIG_DM_I2C */
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+static int lpc32xx_i2c_probe(struct udevice *bus)
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+{
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+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
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+
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+ __i2c_init(dev->base, dev->speed, 0, dev->index);
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+ return 0;
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+}
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+
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+static int lpc32xx_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
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+ u32 chip_flags)
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+{
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+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
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+ return __i2c_probe_chip(dev->base, chip_addr);
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+}
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+
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+static int lpc32xx_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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+ int nmsgs)
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+{
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+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
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+ struct i2c_msg *dmsg, *omsg, dummy;
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+ uint i = 0, address = 0;
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+
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+ memset(&dummy, 0, sizeof(struct i2c_msg));
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+
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+ /* We expect either two messages (one with an offset and one with the
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+ * actual data) or one message (just data)
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+ */
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+ if (nmsgs > 2 || nmsgs == 0) {
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+ debug("%s: Only one or two messages are supported.", __func__);
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+ return -1;
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+ }
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+
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+ omsg = nmsgs == 1 ? &dummy : msg;
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+ dmsg = nmsgs == 1 ? msg : msg + 1;
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+
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+ /* the address is expected to be a uint, not a array. */
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+ address = omsg->buf[0];
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+ for (i = 1; i < omsg->len; i++)
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+ address = (address << 8) + omsg->buf[i];
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+
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+ if (dmsg->flags & I2C_M_RD)
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+ return __i2c_read(dev->base, dmsg->addr, address,
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+ omsg->len, dmsg->buf, dmsg->len);
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+ else
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+ return __i2c_write(dev->base, dmsg->addr, address,
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+ omsg->len, dmsg->buf, dmsg->len);
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+}
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+
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+static int lpc32xx_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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+{
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+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
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+ return __i2c_set_bus_speed(dev->base, speed, dev->index);
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+}
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+
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+static int lpc32xx_i2c_reset(struct udevice *bus)
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+{
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+ struct lpc32xx_i2c_dev *dev = dev_get_platdata(bus);
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+
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+ __i2c_init(dev->base, dev->speed, 0, dev->index);
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+ return 0;
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+}
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+
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+static const struct dm_i2c_ops lpc32xx_i2c_ops = {
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+ .xfer = lpc32xx_i2c_xfer,
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+ .probe_chip = lpc32xx_i2c_probe_chip,
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+ .deblock = lpc32xx_i2c_reset,
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+ .set_bus_speed = lpc32xx_i2c_set_bus_speed,
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+};
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+
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+U_BOOT_DRIVER(i2c_lpc32xx) = {
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+ .id = UCLASS_I2C,
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+ .name = "i2c_lpc32xx",
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+ .probe = lpc32xx_i2c_probe,
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+ .ops = &lpc32xx_i2c_ops,
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+};
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+#endif /* CONFIG_DM_I2C */
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