aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

drivers/clk/aspeed/clk_ast2500.c

@@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
 	const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
 			& SCU_MPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 /*
@@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
 	const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
 			& SCU_HPLL_POST_MASK;
 
-	return (clkin * ((num + 1) / (denum + 1))) / post_div;
+	return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
 }
 
 static ulong ast2500_get_clkin(struct ast2500_scu *scu)