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ARM: zynq: DT: Add missing interrupt for L2 pl310

Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek 10 years ago
parent
commit
d50cb3d64b
1 changed files with 1 additions and 0 deletions
  1. 1 0
      arch/arm/dts/zynq-7000.dtsi

+ 1 - 0
arch/arm/dts/zynq-7000.dtsi

@@ -135,6 +135,7 @@
 		L2: cache-controller@f8f02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xF8F02000 0x1000>;
+			interrupts = <0 2 4>;
 			arm,data-latency = <3 2 2>;
 			arm,tag-latency = <2 2 2>;
 			cache-unified;