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@@ -73,6 +73,46 @@ u32 get_lpuart_clk(void)
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return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
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}
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+#ifdef CONFIG_SYS_LPI2C_IMX
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+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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+{
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+ /* Set parent to FIRC DIV2 clock */
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+ const enum pcc_clk lpi2c_pcc_clks[] = {
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+ PER_CLK_LPI2C4,
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+ PER_CLK_LPI2C5,
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+ PER_CLK_LPI2C6,
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+ PER_CLK_LPI2C7,
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+ };
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+
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+ if (i2c_num < 4 || i2c_num > 7)
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+ return -EINVAL;
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+
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+ if (enable) {
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+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
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+ pcc_clock_sel(lpi2c_pcc_clks[i2c_num - 4], SCG_FIRC_DIV2_CLK);
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+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], true);
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+ } else {
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+ pcc_clock_enable(lpi2c_pcc_clks[i2c_num - 4], false);
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+ }
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+ return 0;
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+}
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+
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+u32 imx_get_i2cclk(unsigned i2c_num)
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+{
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+ const enum pcc_clk lpi2c_pcc_clks[] = {
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+ PER_CLK_LPI2C4,
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+ PER_CLK_LPI2C5,
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+ PER_CLK_LPI2C6,
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+ PER_CLK_LPI2C7,
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+ };
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+
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+ if (i2c_num < 4 || i2c_num > 7)
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+ return 0;
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+
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+ return pcc_clock_get_rate(lpi2c_pcc_clks[i2c_num - 4]);
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+}
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+#endif
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+
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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