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@@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
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dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
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}
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-unsigned int exynos_dwmci_get_clk(int dev_index)
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+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
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{
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- return get_mmc_clk(dev_index);
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+ unsigned long sclk;
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+ int8_t clk_div;
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+
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+ /*
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+ * Since SDCLKIN is divided inside controller by the DIVRATIO
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+ * value set in the CLKSEL register, we need to use the same output
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+ * clock value to calculate the CLKDIV value.
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+ * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
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+ */
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+ clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
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+ & DWMCI_DIVRATIO_MASK) + 1;
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+ sclk = get_mmc_clk(host->dev_index);
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+
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+ return sclk / clk_div;
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}
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static void exynos_dwmci_board_init(struct dwmci_host *host)
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