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@@ -84,6 +84,7 @@
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MVGBE_TX_BURST_SIZE_16_64BIT)
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/* Default port serial control value */
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+#ifndef PORT_SERIAL_CONTROL_VALUE
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#define PORT_SERIAL_CONTROL_VALUE ( \
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MVGBE_FORCE_LINK_PASS | \
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MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
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@@ -101,6 +102,7 @@
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MVGBE_CLR_EXT_LOOPBACK | \
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MVGBE_SET_FULL_DUPLEX_MODE | \
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MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
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+#endif
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/* Tx WRR confoguration macros */
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#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
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