powerpc: remove cogent_8xx, cogent_mpc8260 board support

These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Murray Jensen <Murray.Jensen@csiro.au>

arch/powerpc/cpu/mpc8260/Kconfig

@@ -10,9 +10,6 @@ choice
 config TARGET_ATC
 	bool "Support atc"
 
-config TARGET_COGENT_MPC8260
-	bool "Support cogent_mpc8260"
-
 config TARGET_CPU86
 	bool "Support CPU86"
 
@@ -58,7 +55,6 @@ config TARGET_KM82XX
 endchoice
 
 source "board/atc/Kconfig"
-source "board/cogent/Kconfig"
 source "board/cpu86/Kconfig"
 source "board/cpu87/Kconfig"
 source "board/ep8260/Kconfig"

arch/powerpc/cpu/mpc8260/cpu_init.c

@@ -88,9 +88,7 @@ static void config_8260_ioports (volatile immap_t * immr)
  */
 void cpu_init_f (volatile immap_t * immr)
 {
-#if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	uint sccr;
-#endif
 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 	unsigned long cpu_clk;
 #endif
@@ -141,13 +139,11 @@ void cpu_init_f (volatile immap_t * immr)
 	/* initialize the PIT (4-42) */
 	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
 
-#if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	/* System clock control register (9-8) */
 	sccr = immr->im_clkrst.car_sccr &
 		(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
 	immr->im_clkrst.car_sccr = sccr |
 		(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
-#endif /* !CONFIG_COGENT */
 
 	/*
 	 * Memory Controller:

arch/powerpc/cpu/mpc8260/start.S

@@ -136,14 +136,6 @@ _hrcw_table:
 _start:
 	mfmsr	r5			/* save msr contents		*/
 
-#if defined(CONFIG_COGENT)
-	/* this is what the cogent EPROM does */
-	li	r0, 0
-	mtmsr	r0
-	isync
-	bl	cogent_init_8260
-#endif	/* CONFIG_COGENT */
-
 #if defined(CONFIG_SYS_DEFAULT_IMMR)
 	lis	r3, CONFIG_SYS_IMMR@h
 	ori	r3, r3, CONFIG_SYS_IMMR@l
@@ -379,57 +371,6 @@ int_return:
 	SYNC
 	rfi
 
-#if defined(CONFIG_COGENT)
-
-/*
- * This code initialises the MPC8260 processor core
- * (conforms to PowerPC 603e spec)
- */
-
-	.globl	cogent_init_8260
-cogent_init_8260:
-
-	/* Taken from page 14 of CMA282 manual				*/
-	/*--------------------------------------------------------------*/
-
-	lis	r4, (CONFIG_SYS_IMMR+IM_REGBASE)@h
-	lis	r3, CONFIG_SYS_IMMR@h
-	stw	r3, IM_IMMR@l(r4)
-	lwz	r3, IM_IMMR@l(r4)
-	stw	r3, 0(r0)
-	lis	r3, CONFIG_SYS_SYPCR@h
-	ori	r3, r3, CONFIG_SYS_SYPCR@l
-	stw	r3, IM_SYPCR@l(r4)
-	lwz	r3, IM_SYPCR@l(r4)
-	stw	r3, 4(r0)
-	lis	r3, CONFIG_SYS_SCCR@h
-	ori	r3, r3, CONFIG_SYS_SCCR@l
-	stw	r3, IM_SCCR@l(r4)
-	lwz	r3, IM_SCCR@l(r4)
-	stw	r3, 8(r0)
-
-	/* the rest of this was disassembled from the			*/
-	/* EPROM code that came with my CMA282 CPU module		*/
-	/*--------------------------------------------------------------*/
-
-	lis	r1, 0x1234
-	ori	r1, r1, 0x5678
-	stw	r1, 0x20(r0)
-	lwz	r1, 0x20(r0)
-	stw	r1, 0x24(r0)
-	lwz	r1, 0x24(r0)
-	lis	r3, 0x0e80
-	ori	r3, r3, 0
-	stw	r1, 4(r3)
-	lwz	r1, 4(r3)
-
-	/* Done!							*/
-	/*--------------------------------------------------------------*/
-
-	blr
-
-#endif	/* CONFIG_COGENT */
-
 /*
  * This code initialises the MPC8260 processor core
  * (conforms to PowerPC 603e spec)
@@ -456,11 +397,9 @@ init_8260_core:
 	/*--------------------------------------------------------------*/
 
 	lis	r3, (CONFIG_SYS_IMMR+IM_REGBASE)@h
-#if !defined(CONFIG_COGENT)
 	lis	r4, CONFIG_SYS_SYPCR@h
 	ori	r4, r4, CONFIG_SYS_SYPCR@l
 	stw	r4, IM_SYPCR@l(r3)
-#endif /* !CONFIG_COGENT */
 #if defined(CONFIG_WATCHDOG)
 	li	r4, 21868		/* = 0x556c */
 	sth	r4, IM_SWSR@l(r3)

arch/powerpc/cpu/mpc8xx/Kconfig

@@ -7,9 +7,6 @@ config SYS_CPU
 choice
 	prompt "Target select"
 
-config TARGET_COGENT_MPC8XX
-	bool "Support cogent_mpc8xx"
-
 config TARGET_TQM823L
 	bool "Support TQM823L"
 
@@ -48,7 +45,6 @@ config TARGET_TQM885D
 
 endchoice
 
-source "board/cogent/Kconfig"
 source "board/tqc/tqm8xx/Kconfig"
 
 endmenu

board/cogent/Kconfig

@@ -1,19 +0,0 @@
-if TARGET_COGENT_MPC8260
-
-config SYS_BOARD
-	default "cogent"
-
-config SYS_CONFIG_NAME
-	default "cogent_mpc8260"
-
-endif
-
-if TARGET_COGENT_MPC8XX
-
-config SYS_BOARD
-	default "cogent"
-
-config SYS_CONFIG_NAME
-	default "cogent_mpc8xx"
-
-endif

board/cogent/MAINTAINERS

@@ -1,8 +0,0 @@
-COGENT BOARD
-M:	Murray Jensen <Murray.Jensen@csiro.au>
-S:	Maintained
-F:	board/cogent/
-F:	include/configs/cogent_mpc8260.h
-F:	configs/cogent_mpc8260_defconfig
-F:	include/configs/cogent_mpc8xx.h
-F:	configs/cogent_mpc8xx_defconfig

board/cogent/Makefile

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o

board/cogent/README

@@ -1,118 +0,0 @@
-Cogent Modular Architecture configuration
------------------------------------------
-
-As the name suggests, the Cogent platform is a modular system where
-you have a motherboard into which plugs a cpu module and one or more
-i/o modules. This provides very nice flexibility, but makes the
-configuration task somewhat harder.
-
-The possible Cogent motherboards are:
-
-Code		Config Variable		Description
-----		---------------		-----------
-
-CMA101		CONFIG_CMA101		32MB ram, 2 ser, 1 par, rtc, dipsw,
-					2x16 lcd, eth(?)
-CMA102		CONFIG_CMA102		32MB ram, 2 ser, 1 par, rtc, dipsw,
-					2x16 lcd
-CMA111		CONFIG_CMA111		32MB ram, 1MB flash, 4 ser, 1 par,
-					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
-					10/100TP eth
-CMA120		CONFIG_CMA120		32MB ram, 1MB flash, 4 ser, 1 par,
-					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
-					10/100TP eth, 2xPCMCIA, video/lcd-panel
-CMA150		CONFIG_CMA150		8MB ram, 1MB flash, 2 ser, 1 par, rtc,
-					ps/2 kbd/mse, 2x16 lcd
-
-The possible Cogent PowerPC CPU modules are:
-
-Code		Config Variable		Description
-----		---------------		-----------
-
-CMA278-603EV	CONFIG_CMA278_603EV	PPC603ev CPU, 66MHz clock, 512K EPROM,
-					JTAG/COP
-CMA278-603ER	CONFIG_CMA278_603ER	PPC603er CPU, 66MHz clock, 512K EPROM,
-					JTAG/COP
-CMA278-740	CONFIG_CMA278_740	PPC740 CPU, 66MHz clock, 512K EPROM,
-					JTAG/COP
-CMA280-509	CONFIG_CMA280_509	MPC505/509 CPU, 50MHz clock,
-					512K EPROM, BDM
-CMA282		CONFIG_CMA282		MPC8260 CPU, 66MHz clock, 512K EPROM,
-					JTAG, 16M RAM, 1 x ser (SMC2),
-					1 x 10baseT PHY (SCC4), 1 x 10/100 TP
-					PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1)
-CMA285		CONFIG_CMA285		MPC801 CPU, 33MHz clock, 512K EPROM,
-					BDM
-CMA286-21	CONFIG_CMA286_21	MPC821 CPU, 66MHz clock, 512K EPROM,
-					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
-					1 x 10baseT PHY (SCC2)
-CMA286-60-OLD	CONFIG_CMA286_60_OLD	MPC860 CPU, 33MHz clock, 128K EPROM,
-					BDM
-CMA286-60	CONFIG_CMA286_60	MPC860 CPU, 66MHz clock, 512K EPROM,
-					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
-					1 x 10baseT PHY (SCC2)
-CMA286-60P	CONFIG_CMA286_60P	MPC860P CPU, 66MHz clock, 512K EPROM,
-					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
-					1 x 10baseT PHY (SCC2)
-CMA287-23	CONFIG_CMA287_23	MPC823 CPU, 33MHz clock, 512K EPROM,
-					BDM
-CMA287-50	CONFIG_CMA287_50	MPC850 CPU, 33MHz clock, 512K EPROM,
-					BDM
-
-(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs,
-but we'll worry about those later).
-
-The possible Cogent CMA I/O Modules are:
-
-Code		Config Variable		Description
-----		---------------		-----------
-
-CMA302		CONFIG_CMA302		up to 16M flash, ps/2 keyboard/mouse
-CMA352		CONFIG_CMA352		CMAbus <=> PCI
-
-Currently supported:
-
-	Motherboards:	CMA102
-	CPU Modules:	CMA286-60-OLD
-	I/O Modules:	CMA302 I/O module
-
-To configure, perform the usual U-Boot configuration task of editing
-"include/config_cogent_mpc8xx.h" and reviewing all the options and
-settings in there. In particular, check the chip select values
-installed into the memory controller's various option and base
-registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and
-CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
-into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you
-want the serial console on motherboard serial port A or on one of the
-8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
-(NONE means use Cogent motherboard serial port A).
-
-Then edit the file "cogent/config.mk". Firstly, set CONFIG_SYS_TEXT_BASE to be
-the base address of the EPROM for the CPU module. This should be the
-same as the value selected for CONFIG_SYS_MONITOR_BASE in
-"include/config_cogent_*.h" (in fact, I have made this automatic via
-the -CONFIG_SYS_TEXT_BASE=... option in CPPFLAGS).
-
-Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
-
-$(CMA_MB) is the name of the directory that contains support for your
-motherboard. At this stage, only "cma10x" exists, which supports the
-CMA101 and CMA102 motherboards - but only selected devices, namely
-serial, lcd and dipsw.
-
-$(CMA_IOMS) is a list of zero or more directories that contain
-support for the i/o modules you have installed. At this stage, only
-"cma302" exists, which supports the CMA302 flash i/o module - but
-only the flash part, not the ps/2 keyboard and mouse interfaces.
-
-There should be a make variable for each of the above directories,
-which is the directory name with "_O" appended. This make variable is
-a list of object files to compile from that directory and include in
-the library.
-
-	e.g. cma10x_O = serial.o ...
-
-That's it. Good Luck.
-
-Murray.Jensen@cmst.csiro.au
-August 31, 2000.

board/cogent/README.cma286

@@ -1,69 +0,0 @@
-CPU module revisions
---------------------
-
-My cpu module has the model number "CMA286-60-990526-01". My motherboard
-has the model number "CMA102-32M-990526-01". These are both fairly old,
-and may not reflect current design. In particular, I can see from the
-Cogent web site that the CMA286 has been significantly redesigned - it
-now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports
-(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and
-also the EPROM is 512K.
-
-My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU
-clock is listed as 66MHz, whereas mine is 33.333MHz.
-
-Clocks
-------
-
-Quote from my "CMA286 MPC860/821 User's Manual":
-
-"When setting up the Periodic Interrupt Timer (PIT), be aware that the
-CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed
-a 25MHz clock directly into the MPC860/821. This mode sets the divisor
-for the PIT to be 512. In addition, the Time Base Register (TMB)
-divisor is set to 16."
-
-I interpreted this information to mean that EXTCLK is 25MHz and that at
-power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the
-source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the
-multiplication factor) to 1 (I assume this is what they mean by X1
-mode above). MF=1 means the cpus internal clock runs at the same
-rate as EXTCLK i.e. 25MHz.
-
-Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the
-System Clock and Reset Control register) is set in the cpu initialisation
-code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is
-forced to be 16. This results in TMBCLK=1562500.
-
-One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512,
-PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users
-Manual:
-
-"When used by the real-time clock (RTC), the PITRTCLK source is first
-divided as determined by RTDIV, and then divided in the RTC circuits by
-either 8192 or 9600. Therefore, in order for the RTC to count in
-seconds, the clock source must satisfy:
-
-	(EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1
-
-The RTC will operate with other frequencies, but it will not count in
-units of seconds."
-
-Therefore, the internal RTC of the MPC860 is not going to count in
-seconds, so we must use the motherboard RTC (if we need a RTC).
-
-I presume this means that they do not provide a fixed oscillator for
-OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM,
-RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since
-the CMA286-60 doesn't have this (at least mine doesn't) we can't use
-the code in get_gclk_freq().
-
-Finally, it appears that the internal clock in my CMA286-60 is actually
-33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and
-PITRTCLK=65103.515625 (bloody hell!).
-
-If anyone finds anything wrong with the stuff above, I would appreciate
-an email about it.
-
-Murray Jensen <Murray.Jensen@csiro.au>
-21-Aug-00

board/cogent/dipsw.c

@@ -1,50 +0,0 @@
-#include <common.h>
-#include "dipsw.h"
-
-unsigned char
-dipsw_raw(void)
-{
-    return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val);
-}
-
-unsigned char
-dipsw_cooked(void)
-{
-    unsigned char val1, val2, mask1, mask2;
-
-    val1 = dipsw_raw();
-
-    /*
-     * we want to mirror the bits because the low bit is switch 1 and high
-     * bit is switch 8 and also invert them because 1=off and 0=on, according
-     * to manual.
-     *
-     * this makes the value more intuitive i.e.
-     * - left most, or high, or top, bit is left most switch (1);
-     * - right most, or low, or bottom, bit is right most switch (8)
-     * - a set bit means "on" and a clear bit means "off"
-     */
-
-    val2 = 0;
-    for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1)
-	if ((val1 & mask1) == 0)
-	    val2 |= mask2;
-
-    return (val2);
-}
-
-void
-dipsw_init(void)
-{
-    unsigned char val, mask;
-
-    val = dipsw_cooked();
-
-    printf("|");
-    for (mask = 1 << 7; mask > 0; mask >>= 1)
-	if (val & mask)
-	    printf("on |");
-	else
-	    printf("off|");
-    printf("\n");
-}

board/cogent/dipsw.h

@@ -1,3 +0,0 @@
-extern unsigned char dipsw_raw(void);
-extern unsigned char dipsw_cooked(void);
-extern void dipsw_init(void);

board/cogent/flash.c

@@ -1,633 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include "flash.h"
-#include <linux/compiler.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-
-#if defined(CONFIG_CMA302)
-
-/*
- * probe for the existence of flash at address "addr"
- * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id
- */
-static int
-c302f_probe_word(c302f_addr_t addr)
-{
-	/* reset the flash */
-	*addr = C302F_BNK_CMD_RST;
-
-	/* check the manufacturer id */
-	*addr = C302F_BNK_CMD_RD_ID;
-	if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN)
-		return 1;
-
-	/* check the device id */
-	*addr = C302F_BNK_CMD_RD_ID;
-	if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV)
-		return 2;
-
-#ifdef FLASH_DEBUG
-	{
-		int i;
-
-		printf("\nMaster Lock Config = 0x%08lx\n",
-			*C302F_BNK_ADDR_CFGM(addr));
-		for (i = 0; i < C302F_BNK_NBLOCKS; i++)
-			printf("Block %2d Lock Config = 0x%08lx\n",
-				i, *C302F_BNK_ADDR_CFG(i, addr));
-	}
-#endif
-
-	/* reset the flash again */
-	*addr = C302F_BNK_CMD_RST;
-
-	return 0;
-}
-
-/*
- * probe for Cogent CMA302 flash module at address "base" and store
- * info for any found into flash_info entry "fip". Must find at least
- * one bank.
- */
-static void
-c302f_probe(flash_info_t *fip, c302f_addr_t base)
-{
-	c302f_addr_t addr, eaddr;
-	int nbanks;
-
-	fip->size = 0L;
-	fip->sector_count = 0;
-
-	addr = base;
-	eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS);
-	nbanks = 0;
-
-	while (addr < eaddr) {
-		c302f_addr_t addrw, eaddrw, addrb;
-		int i, osc, nsc;
-
-		addrw = addr;
-		eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
-
-		while (addrw < eaddrw)
-			if (c302f_probe_word(addrw++) != 0)
-				goto out;
-
-		/* bank exists - append info for this bank to *fip */
-		fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5;
-		fip->size += C302F_BNK_SIZE;
-		osc = fip->sector_count;
-		fip->sector_count += C302F_BNK_NBLOCKS;
-		if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT)
-			panic("Too many sectors in flash at address 0x%08lx\n",
-				(unsigned long)base);
-
-		addrb = addr;
-		for (i = osc; i < nsc; i++) {
-			fip->start[i] = (ulong)addrb;
-			fip->protect[i] = 0;
-			addrb = C302F_BNK_ADDR_NEXT_BLK(addrb);
-		}
-
-		addr = C302F_BNK_ADDR_NEXT_BNK(addr);
-		nbanks++;
-	}
-
-out:
-	if (nbanks == 0)
-		panic("ERROR: no flash found at address 0x%08lx\n",
-			(unsigned long)base);
-}
-
-static void
-c302f_reset(flash_info_t *info, int sect)
-{
-	c302f_addr_t addrw, eaddrw;
-
-	addrw = (c302f_addr_t)info->start[sect];
-	eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
-
-	while (addrw < eaddrw) {
-#ifdef FLASH_DEBUG
-		printf("  writing reset cmd to addr 0x%08lx\n",
-			(unsigned long)addrw);
-#endif
-		*addrw = C302F_BNK_CMD_RST;
-		addrw++;
-	}
-}
-
-static void
-c302f_erase_init(flash_info_t *info, int sect)
-{
-	c302f_addr_t addrw, saddrw, eaddrw;
-	int flag;
-
-#ifdef FLASH_DEBUG
-	printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG);
-	printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1);
-	printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2);
-	printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT);
-	printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST);
-	printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY);
-	printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR);
-#endif
-
-	saddrw = (c302f_addr_t)info->start[sect];
-	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
-
-#ifdef FLASH_DEBUG
-	printf("erasing sector %d, start addr = 0x%08lx "
-		"(bank next word addr = 0x%08lx)\n", sect,
-		(unsigned long)saddrw, (unsigned long)eaddrw);
-#endif
-
-	/* Disable intrs which might cause a timeout here */
-	flag = disable_interrupts();
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-#ifdef FLASH_DEBUG
-		printf("  writing erase cmd to addr 0x%08lx\n",
-			(unsigned long)addrw);
-#endif
-		*addrw = C302F_BNK_CMD_ERASE1;
-		*addrw = C302F_BNK_CMD_ERASE2;
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-}
-
-static int
-c302f_erase_poll(flash_info_t *info, int sect)
-{
-	c302f_addr_t addrw, saddrw, eaddrw;
-	int sectdone, haderr;
-
-	saddrw = (c302f_addr_t)info->start[sect];
-	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
-
-	sectdone = 1;
-	haderr = 0;
-
-	for (addrw = saddrw; addrw < eaddrw; addrw++) {
-		c302f_word_t stat = *addrw;
-
-#ifdef FLASH_DEBUG
-		printf("  checking status at addr "
-			"0x%08lx [0x%08lx]\n",
-			(unsigned long)addrw, stat);
-#endif
-		if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY)
-			sectdone = 0;
-		else if ((stat & C302F_BNK_STAT_ERR) != 0) {
-			printf(" failed on sector %d "
-				"(stat = 0x%08lx) at "
-				"address 0x%08lx\n",
-				sect, stat,
-				(unsigned long)addrw);
-			*addrw = C302F_BNK_CMD_CLR_STAT;
-			haderr = 1;
-		}
-	}
-
-	if (haderr)
-		return (-1);
-	else
-		return (sectdone);
-}
-
-static int
-c302f_write_word(c302f_addr_t addr, c302f_word_t value)
-{
-	c302f_word_t stat;
-	ulong start;
-	int flag, retval;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	*addr = C302F_BNK_CMD_PROG;
-
-	*addr = value;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	retval = 0;
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	do {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			retval = 1;
-			goto done;
-		}
-		stat = *addr;
-	} while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY);
-
-	if ((stat & C302F_BNK_STAT_ERR) != 0) {
-		printf("flash program failed (stat = 0x%08lx) "
-			"at address 0x%08lx\n", (ulong)stat, (ulong)addr);
-		*addr = C302F_BNK_CMD_CLR_STAT;
-		retval = 3;
-	}
-
-done:
-	/* reset to read mode */
-	*addr = C302F_BNK_CMD_RST;
-
-	return (retval);
-}
-
-#endif	/* CONFIG_CMA302 */
-
-unsigned long
-flash_init(void)
-{
-	unsigned long total;
-	int i;
-	__maybe_unused flash_info_t *fip;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	fip = &flash_info[0];
-	total = 0L;
-
-#if defined(CONFIG_CMA302)
-	c302f_probe(fip, (c302f_addr_t)CONFIG_SYS_FLASH_BASE);
-	total += fip->size;
-	fip++;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-	/* not yet ...
-	cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE);
-	total += fip->size;
-	fip++;
-	*/
-#endif
-
-	/*
-	 * protect monitor and environment sectors
-	 */
-
-#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-	return total;
-}
-
-/*-----------------------------------------------------------------------
- */
-void
-flash_print_info(flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F008S5:	printf ("28F008S5\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 4) == 0)
-			printf ("\n   ");
-		printf (" %2d - %08lX%s", i,
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
-	int prot, sect, haderr;
-	ulong start, now, last;
-	void (*erase_init)(flash_info_t *, int);
-	int (*erase_poll)(flash_info_t *, int);
-	void (*reset)(flash_info_t *, int);
-	int rcode = 0;
-
-#ifdef FLASH_DEBUG
-	printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
-		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
-		(info - flash_info) + 1);
-	flash_print_info(info);
-#endif
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	switch (info->flash_id) {
-
-#if defined(CONFIG_CMA302)
-	case FLASH_MAN_INTEL|FLASH_28F008S5:
-		erase_init = c302f_erase_init;
-		erase_poll = c302f_erase_poll;
-		reset = c302f_reset;
-		break;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-	case FLASH_MAN_INTEL|FLASH_28F800_B:
-	case FLASH_MAN_AMD|FLASH_AM29F800B:
-		/* not yet ...
-		erase_init = cmbf_erase_init;
-		erase_poll = cmbf_erase_poll;
-		reset = cmbf_reset;
-		break;
-		*/
-#endif
-
-	default:
-		printf ("Flash type %08lx not supported - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sector%s will not be erased!\n",
-			prot, (prot > 1 ? "s" : ""));
-	}
-
-	start = get_timer (0);
-	last = 0;
-	haderr = 0;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			ulong estart;
-			int sectdone;
-
-			(*erase_init)(info, sect);
-
-			/* wait at least 80us - let's wait 1 ms */
-			udelay (1000);
-
-			estart = get_timer(start);
-
-			do {
-				now = get_timer(start);
-
-				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout (sect %d)\n", sect);
-					haderr = 1;
-					break;
-				}
-
-#ifndef FLASH_DEBUG
-				/* show that we're waiting */
-				if ((now - last) > 1000) { /* every second */
-					putc ('.');
-					last = now;
-				}
-#endif
-
-				sectdone = (*erase_poll)(info, sect);
-
-				if (sectdone < 0) {
-					haderr = 1;
-					break;
-				}
-
-			} while (!sectdone);
-
-			if (haderr)
-				break;
-		}
-	}
-
-	if (haderr > 0) {
-		printf (" failed\n");
-		rcode = 1;
-	}
-	else
-		printf (" done\n");
-
-	/* reset to read mode */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			(*reset)(info, sect);
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - write error
- */
-
-int
-write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-	ulong start, now, last;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	start = get_timer (0);
-	last = 0;
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-
-		/* show that we're waiting */
-		now = get_timer(start);
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 3 - write error
- */
-static int
-write_word(flash_info_t *info, ulong dest, ulong data)
-{
-	int retval;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*(ulong *)dest & data) != data) {
-		return (2);
-	}
-
-	switch (info->flash_id) {
-
-#if defined(CONFIG_CMA302)
-	case FLASH_MAN_INTEL|FLASH_28F008S5:
-		retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data);
-		break;
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-	case FLASH_MAN_INTEL|FLASH_28F800_B:
-	case FLASH_MAN_AMD|FLASH_AM29F800B:
-		/* not yet ...
-		retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data);
-		*/
-		retval = 3;
-		break;
-#endif
-
-	default:
-		printf ("Flash type %08lx not supported - aborted\n",
-			info->flash_id);
-		retval = 3;
-		break;
-	}
-
-	return (retval);
-}
-
-/*-----------------------------------------------------------------------
- */

board/cogent/flash.h

@@ -1,305 +0,0 @@
-/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/
-
-/* register addresses, valid only following a I8S5_CMD_RD_ID command */
-#define I8S5_ADDR_MAN	0x00000	/* manufacturer's id */
-#define I8S5_ADDR_DEV	0x00001	/* device id */
-#define I8S5_ADDR_CFGM	0x00003	/* master lock configuration */
-#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
-
-/* Commands */
-#define I8S5_CMD_RST	0xFF	/* reset flash */
-#define I8S5_CMD_RD_ID	0x90	/* read the id and lock bits */
-#define I8S5_CMD_RD_STAT 0x70	/* read the status register */
-#define I8S5_CMD_CLR_STAT 0x50	/* clear the staus register */
-#define I8S5_CMD_ERASE1	0x20	/* first word for block erase */
-#define I8S5_CMD_ERASE2	0xD0	/* second word for block erase */
-#define I8S5_CMD_PROG	0x40	/* program word command */
-#define I8S5_CMD_LOCK	0x60	/* first word for all lock commands */
-#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */
-#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */
-#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */
-
-/* status register bits */
-#define I8S5_STAT_DPS	0x02	/* Device Protect Status */
-#define I8S5_STAT_PSS	0x04	/* Program Suspend Status */
-#define I8S5_STAT_VPPS	0x08	/* VPP Status */
-#define I8S5_STAT_PSLBS	0x10	/* Program and Set Lock Bit Status */
-#define I8S5_STAT_ECLBS	0x20	/* Erase and Clear Lock Bit Status */
-#define I8S5_STAT_ESS	0x40	/* Erase Suspend Status */
-#define I8S5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
-
-#define I8S5_STAT_ERR	(I8S5_STAT_VPPS | I8S5_STAT_DPS | \
-			    I8S5_STAT_ECLBS | I8S5_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define I8S5_RD_ID_LOCK	0x01	/* Bit 0 of each byte */
-#define I8S5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
-#define I8S5_RD_ID_DEV	0xA6	/* Device code = 0xA6, 28F008S5 */
-
-/* dimensions */
-#define I8S5_NBLOCKS	16		/* a 28F008S5 consists of 16 blocks */
-#define I8S5_BLKSZ	(64*1024)	/* of 64Kbyte each */
-#define I8S5_SIZE	(I8S5_BLKSZ * I8S5_NBLOCKS)
-
-/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/
-
-/* register addresses, valid only following a I8S5_CMD_RD_ID command */
-#define I8B5_ADDR_MAN	0x00000	/* manufacturer's id */
-#define I8B5_ADDR_DEV	0x00001	/* device id */
-
-/* Commands */
-#define I8B5_CMD_RST	0xFF	/* reset flash */
-#define I8B5_CMD_RD_ID	0x90	/* read the id and lock bits */
-#define I8B5_CMD_RD_STAT 0x70	/* read the status register */
-#define I8B5_CMD_CLR_STAT 0x50	/* clear the staus register */
-#define I8B5_CMD_ERASE1	0x20	/* first word for block erase */
-#define I8B5_CMD_ERASE2	0xD0	/* second word for block erase */
-#define I8B5_CMD_PROG	0x40	/* program word command */
-
-/* status register bits */
-#define I8B5_STAT_VPPS	0x08	/* VPP Status */
-#define I8B5_STAT_DWS	0x10	/* Program and Set Lock Bit Status */
-#define I8B5_STAT_ES	0x20	/* Erase and Clear Lock Bit Status */
-#define I8B5_STAT_ESS	0x40	/* Erase Suspend Status */
-#define I8B5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
-
-#define I8B5_STAT_ERR	(I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES)
-
-/* ID Configuration */
-#define I8B5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
-#define I8B5_RD_ID_DEV1	0x889D	/* Device code = 0x889D, 28F800B5 */
-
-/* dimensions */
-#define I8B5_NBLOCKS	8		/* a 28F008S5 consists of 16 blocks */
-#define I8B5_BLKSZ	(128*1024)	/* of 64Kbyte each */
-#define I8B5_SIZE	(I8B5_BLKSZ * I8B5_NBLOCKS)
-
-/****************** DEFINES for Cogent CMA302 Flash **************************/
-
-/*
- * Quoted from the CMA302 manual:
- *
- * Although the CMA302 supports 64-bit reads, all writes must be done with
- * word size only. When programming the CMA302, the FLASH devices appear as 2
- * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four
- * 28F008S5 devices. The first bank is accessed when the word address is even,
- * while the second bank is accessed when the word address is odd. This must
- * be taken into account when programming the desired word. Also, when locking
- * blocks, software must lock both banks. The CMA302 does not directly support
- * byte writing.  Programming and/or erasing individual bytes is done with
- * selective use of the Write Command.  By not placing the Write Command value
- * on a particular byte lane, that byte will not be written with the following
- * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are
- * two 28F008S5 devices, one for each bank or every other word.
- *
- * End quote.
- *
- * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The
- * chips are arranged on the CMA302 in multiples of two banks, each bank having
- * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e.
- * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3)
- * going to each of the 4 chips and the word address selecting the bank, even
- * being the low bank and odd the high bank. For 64bit reads, both banks are
- * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5
- * consists of 16 64Kbyte "block"s. Before programming a byte, the block that
- * the byte resides within must be erased. So if you want to program contiguous
- * memory locations, you must erase all 8 chips at the same time. i.e. the
- * flash on the CMA302 can be viewed as a number of 512Kbyte blocks.
- *
- * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas
- * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks.
- */
-
-typedef unsigned long c302f_word_t;	/* 32 or 64 bit unsigned integer */
-typedef volatile c302f_word_t *c302f_addr_t;
-typedef unsigned long c302f_size_t;	/* want this big - at least 32 bit */
-
-/* layout of banks on cma302 board */
-#define C302F_BNK_WIDTH		8	/* each bank is 8 chips wide */
-#define C302F_BNK_WSHIFT	3	/* log base 2 of C302F_BNK_WIDTH */
-#define C302F_BNK_NBLOCKS	I8S5_NBLOCKS
-#define C302F_BNK_BLKSZ		(I8S5_BLKSZ * C302F_BNK_WIDTH)
-#define C302F_BNK_SIZE		(I8S5_SIZE * C302F_BNK_WIDTH)
-
-#define C302F_MAX_BANKS		2	/* up to 2 banks (8M each) on CMA302 */
-
-/* align addresses and sizes to bank boundaries */
-#define C302F_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
-				    & ~(C302F_BNK_WIDTH - 1)))
-#define C302F_BNK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BNK_ADDR_ALIGN( \
-				    (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1)))
-
-/* align addresses and sizes to block boundaries */
-#define C302F_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
-				    & ~(C302F_BNK_BLKSZ - 1)))
-#define C302F_BLK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BLK_ADDR_ALIGN( \
-				    (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1)))
-
-/* add a byte offset to a flash address */
-#define C302F_ADDR_ADD_BYTEOFF(a,o) \
-				(c302f_addr_t)((c302f_size_t)(a) + (o))
-
-/* get base address of bank b, given flash base address a */
-#define C302F_BNK_ADDR_BASE(a,b) \
-				C302F_ADDR_ADD_BYTEOFF((a), \
-				    (c302f_size_t)(b) * C302F_BNK_SIZE)
-
-/* adjust an address a (within a bank) to next word, block or bank */
-#define C302F_BNK_ADDR_NEXT_WORD(a) \
-				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH)
-#define C302F_BNK_ADDR_NEXT_BLK(a) \
-				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ)
-#define C302F_BNK_ADDR_NEXT_BNK(a) \
-				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define C302F_BNK_ADDR_I8S5REG(a,r) \
-				C302F_ADDR_ADD_BYTEOFF((a), \
-				    (r) << C302F_BNK_WSHIFT)
-
-/* make a bank representation for each chip address */
-
-#define C302F_BNK_ADDR_MAN(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
-#define C302F_BNK_ADDR_DEV(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
-#define C302F_BNK_ADDR_CFGM(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
-#define C302F_BNK_ADDR_CFG(b,a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the c302f_word_t type
- */
-#define C302F_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
-				    ((unsigned long)(o) << 16) | \
-				    ((unsigned long)(o) << 8) | \
-				    (unsigned long)(o))
-
-/* make a bank representation for each chip cmd/stat/rd value */
-
-/* Commands */
-#define C302F_BNK_CMD_RST	C302F_FILL_WORD(I8S5_CMD_RST)
-#define C302F_BNK_CMD_RD_ID	C302F_FILL_WORD(I8S5_CMD_RD_ID)
-#define C302F_BNK_CMD_RD_STAT	C302F_FILL_WORD(I8S5_CMD_RD_STAT)
-#define C302F_BNK_CMD_CLR_STAT	C302F_FILL_WORD(I8S5_CMD_CLR_STAT)
-#define C302F_BNK_CMD_ERASE1	C302F_FILL_WORD(I8S5_CMD_ERASE1)
-#define C302F_BNK_CMD_ERASE2	C302F_FILL_WORD(I8S5_CMD_ERASE2)
-#define C302F_BNK_CMD_PROG	C302F_FILL_WORD(I8S5_CMD_PROG)
-#define C302F_BNK_CMD_LOCK	C302F_FILL_WORD(I8S5_CMD_LOCK)
-#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK)
-#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR)
-#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define C302F_BNK_STAT_DPS	C302F_FILL_WORD(I8S5_STAT_DPS)
-#define C302F_BNK_STAT_PSS	C302F_FILL_WORD(I8S5_STAT_PSS)
-#define C302F_BNK_STAT_VPPS	C302F_FILL_WORD(I8S5_STAT_VPPS)
-#define C302F_BNK_STAT_PSLBS	C302F_FILL_WORD(I8S5_STAT_PSLBS)
-#define C302F_BNK_STAT_ECLBS	C302F_FILL_WORD(I8S5_STAT_ECLBS)
-#define C302F_BNK_STAT_ESS	C302F_FILL_WORD(I8S5_STAT_ESS)
-#define C302F_BNK_STAT_RDY	C302F_FILL_WORD(I8S5_STAT_RDY)
-
-#define C302F_BNK_STAT_ERR	C302F_FILL_WORD(I8S5_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define C302F_BNK_RD_ID_LOCK	C302F_FILL_WORD(I8S5_RD_ID_LOCK)
-#define C302F_BNK_RD_ID_MAN	C302F_FILL_WORD(I8S5_RD_ID_MAN)
-#define C302F_BNK_RD_ID_DEV	C302F_FILL_WORD(I8S5_RD_ID_DEV)
-
-/*************** DEFINES for Cogent Motherboard Flash ************************/
-
-typedef unsigned short cmbf_word_t;	/* 16 bit unsigned integer */
-typedef volatile cmbf_word_t *cmbf_addr_t;
-typedef unsigned long cmbf_size_t;	/* want this big - at least 32 bit */
-
-/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */
-#define CMBF_BNK_WIDTH		1	/* each bank is one chip wide */
-#define CMBF_BNK_WSHIFT	0	/* log base 2 of CMBF_BNK_WIDTH */
-#define CMBF_BNK_NBLOCKS	I8B5_NBLOCKS
-#define CMBF_BNK_BLKSZ		(I8B5_BLKSZ * CMBF_BNK_WIDTH)
-#define CMBF_BNK_SIZE		(I8B5_SIZE * CMBF_BNK_WIDTH)
-
-#define CMBF_MAX_BANKS		1	/* only 1 x 1Mbyte bank on cogent m/b */
-
-/* align addresses and sizes to bank boundaries */
-#define CMBF_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
-				    & ~(CMBF_BNK_WIDTH - 1)))
-#define CMBF_BNK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \
-				    (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1)))
-
-/* align addresses and sizes to block boundaries */
-#define CMBF_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
-				    & ~(CMBF_BNK_BLKSZ - 1)))
-#define CMBF_BLK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \
-				    (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1)))
-
-/* add a byte offset to a flash address */
-#define CMBF_ADDR_ADD_BYTEOFF(a,o) \
-				(c302f_addr_t)((c302f_size_t)(a) + (o))
-
-/* get base address of bank b, given flash base address a */
-#define CMBF_BNK_ADDR_BASE(a,b) \
-				CMBF_ADDR_ADD_BYTEOFF((a), \
-				    (c302f_size_t)(b) * CMBF_BNK_SIZE)
-
-/* adjust an address a (within a bank) to next word, block or bank */
-#define CMBF_BNK_ADDR_NEXT_WORD(a) \
-				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH)
-#define CMBF_BNK_ADDR_NEXT_BLK(a) \
-				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ)
-#define CMBF_BNK_ADDR_NEXT_BNK(a) \
-				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define CMBF_BNK_ADDR_I8B5REG(a,r) \
-				CMBF_ADDR_ADD_BYTEOFF((a), \
-				    (r) << CMBF_BNK_WSHIFT)
-
-/* make a bank representation for each chip address */
-
-#define CMBF_BNK_ADDR_MAN(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
-#define CMBF_BNK_ADDR_DEV(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
-#define CMBF_BNK_ADDR_CFGM(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
-#define CMBF_BNK_ADDR_CFG(b,a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the c302f_word_t type
- */
-#define CMBF_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
-				    ((unsigned long)(o) << 16) | \
-				    ((unsigned long)(o) << 8) | \
-				    (unsigned long)(o))
-
-/* make a bank representation for each chip cmd/stat/rd value */
-
-/* Commands */
-#define CMBF_BNK_CMD_RST	CMBF_FILL_WORD(I8B5_CMD_RST)
-#define CMBF_BNK_CMD_RD_ID	CMBF_FILL_WORD(I8B5_CMD_RD_ID)
-#define CMBF_BNK_CMD_RD_STAT	CMBF_FILL_WORD(I8B5_CMD_RD_STAT)
-#define CMBF_BNK_CMD_CLR_STAT	CMBF_FILL_WORD(I8B5_CMD_CLR_STAT)
-#define CMBF_BNK_CMD_ERASE1	CMBF_FILL_WORD(I8B5_CMD_ERASE1)
-#define CMBF_BNK_CMD_ERASE2	CMBF_FILL_WORD(I8B5_CMD_ERASE2)
-#define CMBF_BNK_CMD_PROG	CMBF_FILL_WORD(I8B5_CMD_PROG)
-#define CMBF_BNK_CMD_LOCK	CMBF_FILL_WORD(I8B5_CMD_LOCK)
-#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK)
-#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR)
-#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define CMBF_BNK_STAT_DPS	CMBF_FILL_WORD(I8B5_STAT_DPS)
-#define CMBF_BNK_STAT_PSS	CMBF_FILL_WORD(I8B5_STAT_PSS)
-#define CMBF_BNK_STAT_VPPS	CMBF_FILL_WORD(I8B5_STAT_VPPS)
-#define CMBF_BNK_STAT_PSLBS	CMBF_FILL_WORD(I8B5_STAT_PSLBS)
-#define CMBF_BNK_STAT_ECLBS	CMBF_FILL_WORD(I8B5_STAT_ECLBS)
-#define CMBF_BNK_STAT_ESS	CMBF_FILL_WORD(I8B5_STAT_ESS)
-#define CMBF_BNK_STAT_RDY	CMBF_FILL_WORD(I8B5_STAT_RDY)
-
-#define CMBF_BNK_STAT_ERR	CMBF_FILL_WORD(I8B5_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define CMBF_BNK_RD_ID_LOCK	CMBF_FILL_WORD(I8B5_RD_ID_LOCK)
-#define CMBF_BNK_RD_ID_MAN	CMBF_FILL_WORD(I8B5_RD_ID_MAN)
-#define CMBF_BNK_RD_ID_DEV	CMBF_FILL_WORD(I8B5_RD_ID_DEV)

board/cogent/kbm.c

@@ -1,3 +0,0 @@
-/* keyboard/mouse not implemented yet */
-
-int cma_kbm_not_implemented = 1;

board/cogent/lcd.c

@@ -1,245 +0,0 @@
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/*      hal_diag.c */
-/* */
-/*      HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License.  You may obtain a copy of the License at */
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus.  Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s):    nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date:         1999-03-23 */
-/* Purpose:      HAL diagnostic output */
-/* Description:  Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/*----------------------------------------------------------------------------- */
-/* Cogent board specific LCD code */
-
-#include <common.h>
-#include <stdarg.h>
-#include "lcd.h"
-
-static char lines[2][LCD_LINE_LENGTH+1];
-static int curline;
-static int linepos;
-static int heartbeat_active;
-/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
-/* pad to the right with spaces if necessary */
-static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent  ";
-static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
-
-static inline unsigned char
-lcd_read_status(cma_mb_lcd *clp)
-{
-    /* read the Busy Status Register */
-    return (cma_mb_reg_read(&clp->lcd_bsr));
-}
-
-static inline void
-lcd_wait_not_busy(cma_mb_lcd *clp)
-{
-    /*
-     * wait for not busy
-     * Note: It seems that the LCD isn't quite ready to process commands
-     * when it clears the BUSY flag. Reading the status address an extra
-     * time seems to give it enough breathing room.
-     */
-
-    while (lcd_read_status(clp) & LCD_STAT_BUSY)
-	;
-
-    (void)lcd_read_status(clp);
-}
-
-static inline void
-lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
-{
-    lcd_wait_not_busy(clp);
-
-    /* write the Command Register */
-    cma_mb_reg_write(&clp->lcd_cmd, cmd);
-}
-
-static inline void
-lcd_write_data(cma_mb_lcd *clp, unsigned char data)
-{
-    lcd_wait_not_busy(clp);
-
-    /* write the Current Character Register */
-    cma_mb_reg_write(&clp->lcd_ccr, data);
-}
-
-static inline void
-lcd_dis(int addr, char *string)
-{
-    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
-    int pos, linelen;
-
-    linelen = LCD_LINE_LENGTH;
-    if (heartbeat_active && addr == LCD_LINE0)
-	linelen--;
-
-    lcd_write_command(clp, LCD_CMD_ADD + addr);
-    for (pos = 0; *string != '\0' && pos < linelen; pos++)
-	lcd_write_data(clp, *string++);
-}
-
-void
-lcd_init(void)
-{
-    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
-    int i;
-
-    /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
-    lcd_write_command(clp, LCD_CMD_MODE);
-
-    /* turn the LCD display on */
-    lcd_write_command(clp, LCD_CMD_DON);
-
-    curline = 0;
-    linepos = 0;
-
-    for (i = 0; i < LCD_LINE_LENGTH; i++) {
-	lines[0][i] = init_line0[i];
-	lines[1][i] = init_line1[i];
-    }
-
-    lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
-
-    lcd_dis(LCD_LINE0, lines[0]);
-    lcd_dis(LCD_LINE1, lines[1]);
-
-    printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
-}
-
-void
-lcd_write_char(const char c)
-{
-    int i, linelen;
-
-    /* ignore CR */
-    if (c == '\r')
-	return;
-
-    linelen = LCD_LINE_LENGTH;
-    if (heartbeat_active && curline == 0)
-	linelen--;
-
-    if (c == '\n') {
-	lcd_dis(LCD_LINE0, &lines[curline^1][0]);
-	lcd_dis(LCD_LINE1, &lines[curline][0]);
-
-	/* Do a line feed */
-	curline ^= 1;
-	linelen = LCD_LINE_LENGTH;
-	if (heartbeat_active && curline == 0)
-	    linelen--;
-	linepos = 0;
-
-	for (i = 0; i < linelen; i++)
-	    lines[curline][i] = ' ';
-
-	return;
-    }
-
-    /* Only allow to be output if there is room on the LCD line */
-    if (linepos < linelen)
-	lines[curline][linepos++] = c;
-}
-
-void
-lcd_flush(void)
-{
-    lcd_dis(LCD_LINE1, &lines[curline][0]);
-}
-
-void
-lcd_write_string(const char *s)
-{
-    char *p;
-
-    for (p = (char *)s; *p != '\0'; p++)
-	lcd_write_char(*p);
-}
-
-void
-lcd_printf(const char *fmt, ...)
-{
-    va_list args;
-    char buf[CONFIG_SYS_PBSIZE];
-
-    va_start(args, fmt);
-    (void)vsprintf(buf, fmt, args);
-    va_end(args);
-
-    lcd_write_string(buf);
-}
-
-void
-lcd_heartbeat(void)
-{
-    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
-#if 0
-    static char rotchars[] = { '|', '/', '-', '\\' };
-#else
-    /* HD44780 Rom Code A00 has no backslash */
-    static char rotchars[] = { '|', '/', '-', '\315' };
-#endif
-    static int rotator_index = 0;
-
-    heartbeat_active = 1;
-
-    /* write the address */
-    lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
-
-    /* write the next char in the sequence */
-    lcd_write_data(clp, rotchars[rotator_index]);
-
-    if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
-	rotator_index = 0;
-}
-
-#ifdef CONFIG_SHOW_ACTIVITY
-void board_show_activity (ulong timestamp)
-{
-#ifdef CONFIG_STATUS_LED
-	if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0)
-		lcd_heartbeat ();
-#endif
-}
-
-void show_activity(int arg)
-{
-}
-#endif

board/cogent/lcd.h

@@ -1,84 +0,0 @@
-/* most of this is taken from the file */
-/* hal/powerpc/cogent/current/src/hal_diag.c in the */
-/* Cygnus eCos source. Here is the copyright notice: */
-/* */
-/*============================================================================= */
-/* */
-/*      hal_diag.c */
-/* */
-/*      HAL diagnostic output code */
-/* */
-/*============================================================================= */
-/*####COPYRIGHTBEGIN#### */
-/* */
-/* ------------------------------------------- */
-/* The contents of this file are subject to the Cygnus eCos Public License */
-/* Version 1.0 (the "License"); you may not use this file except in */
-/* compliance with the License.  You may obtain a copy of the License at */
-/* http://sourceware.cygnus.com/ecos */
-/* */
-/* Software distributed under the License is distributed on an "AS IS" */
-/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
-/* License for the specific language governing rights and limitations under */
-/* the License. */
-/* */
-/* The Original Code is eCos - Embedded Cygnus Operating System, released */
-/* September 30, 1998. */
-/* */
-/* The Initial Developer of the Original Code is Cygnus.  Portions created */
-/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
-/* ------------------------------------------- */
-/* */
-/*####COPYRIGHTEND#### */
-/*============================================================================= */
-/*#####DESCRIPTIONBEGIN#### */
-/* */
-/* Author(s):    nickg, jskov */
-/* Contributors: nickg, jskov */
-/* Date:         1999-03-23 */
-/* Purpose:      HAL diagnostic output */
-/* Description:  Implementations of HAL diagnostic output support. */
-/* */
-/*####DESCRIPTIONEND#### */
-/* */
-/*============================================================================= */
-
-/* FEMA 162B 16 character x 2 line LCD */
-
-/* status register bit definitions */
-#define LCD_STAT_BUSY	0x80	/* 1 = display busy */
-#define LCD_STAT_ADD	0x7F	/* bits 0-6 return current display address */
-
-/* command register definitions */
-#define LCD_CMD_RST	0x01	/* clear entire display and reset display addr */
-#define LCD_CMD_HOME	0x02	/* reset display address and reset any shifting */
-#define LCD_CMD_ECL	0x04	/* move cursor left one pos on next data write */
-#define LCD_CMD_ESL	0x05	/* shift display left one pos on next data write */
-#define LCD_CMD_ECR	0x06	/* move cursor right one pos on next data write */
-#define LCD_CMD_ESR	0x07	/* shift disp right one pos on next data write */
-#define LCD_CMD_DOFF	0x08	/* display off, cursor off, blinking off */
-#define LCD_CMD_BL	0x09	/* blink character at current cursor position */
-#define LCD_CMD_CUR	0x0A	/* enable cursor on */
-#define LCD_CMD_DON	0x0C	/* turn display on */
-#define LCD_CMD_CL	0x10	/* move cursor left one position */
-#define LCD_CMD_SL	0x14	/* shift display left one position */
-#define LCD_CMD_CR	0x18	/* move cursor right one position */
-#define LCD_CMD_SR	0x1C	/* shift display right one position */
-#define LCD_CMD_MODE	0x38	/* sets 8 bits, 2 lines, 5x7 characters */
-#define LCD_CMD_ACG	0x40	/* bits 0-5 sets character generator address */
-#define LCD_CMD_ADD	0x80	/* bits 0-6 sets display data addr to line 1 + */
-
-/* LCD status values */
-#define LCD_OK		0x00
-#define LCD_ERR		0x01
-
-#define LCD_LINE0	0x00
-#define LCD_LINE1	0x40
-
-#define LCD_LINE_LENGTH	16
-
-extern void lcd_init(void);
-extern void lcd_write_char(const char);
-extern void lcd_flush(void);
-extern void lcd_write_string(const char *);
-extern void lcd_printf(const char *, ...);

board/cogent/mb.c

@@ -1,280 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include "dipsw.h"
-#include "lcd.h"
-#include "rtc.h"
-#include "par.h"
-#include "pci.h"
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_MPC8260)
-
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-	/* Port A configuration */
-	{			/*            conf ppar psor pdir podr pdat */
-	 /* PA31 */ {0, 0, 0, 0, 0, 0},
-	 /* PA30 */ {0, 0, 0, 0, 0, 0},
-	 /* PA29 */ {0, 0, 0, 0, 0, 0},
-	 /* PA28 */ {0, 0, 0, 0, 0, 0},
-	 /* PA27 */ {0, 0, 0, 0, 0, 0},
-	 /* PA26 */ {0, 0, 0, 0, 0, 0},
-	 /* PA25 */ {0, 0, 0, 0, 0, 0},
-	 /* PA24 */ {0, 0, 0, 0, 0, 0},
-	 /* PA23 */ {0, 0, 0, 0, 0, 0},
-	 /* PA22 */ {0, 0, 0, 0, 0, 0},
-	 /* PA21 */ {0, 0, 0, 0, 0, 0},
-	 /* PA20 */ {0, 0, 0, 0, 0, 0},
-	 /* PA19 */ {0, 0, 0, 0, 0, 0},
-	 /* PA18 */ {0, 0, 0, 0, 0, 0},
-	 /* PA17 */ {0, 0, 0, 0, 0, 0},
-	 /* PA16 */ {0, 0, 0, 0, 0, 0},
-	 /* PA15 */ {0, 0, 0, 0, 0, 0},
-	 /* PA14 */ {0, 0, 0, 0, 0, 0},
-	 /* PA13 */ {0, 0, 0, 0, 0, 0},
-	 /* PA12 */ {0, 0, 0, 0, 0, 0},
-	 /* PA11 */ {0, 0, 0, 0, 0, 0},
-	 /* PA10 */ {0, 0, 0, 0, 0, 0},
-					/* PA9  */ {1, 1, 0, 1, 0, 0},
-					/* SMC2 TXD */
-					/* PA8  */ {1, 1, 0, 0, 0, 0},
-					/* SMC2 RXD */
-	 /* PA7  */ {0, 0, 0, 0, 0, 0},
-	 /* PA6  */ {0, 0, 0, 0, 0, 0},
-	 /* PA5  */ {0, 0, 0, 0, 0, 0},
-	 /* PA4  */ {0, 0, 0, 0, 0, 0},
-	 /* PA3  */ {0, 0, 0, 0, 0, 0},
-	 /* PA2  */ {0, 0, 0, 0, 0, 0},
-	 /* PA1  */ {0, 0, 0, 0, 0, 0},
-	 /* PA0  */ {0, 0, 0, 0, 0, 0}
-	 },
-
-
-	{			/*            conf ppar psor pdir podr pdat */
-	 /* PB31 */ {0, 0, 0, 0, 0, 0},
-	 /* PB30 */ {0, 0, 0, 0, 0, 0},
-	 /* PB29 */ {0, 0, 0, 0, 0, 0},
-	 /* PB28 */ {0, 0, 0, 0, 0, 0},
-	 /* PB27 */ {0, 0, 0, 0, 0, 0},
-	 /* PB26 */ {0, 0, 0, 0, 0, 0},
-	 /* PB25 */ {0, 0, 0, 0, 0, 0},
-	 /* PB24 */ {0, 0, 0, 0, 0, 0},
-	 /* PB23 */ {0, 0, 0, 0, 0, 0},
-	 /* PB22 */ {0, 0, 0, 0, 0, 0},
-	 /* PB21 */ {0, 0, 0, 0, 0, 0},
-	 /* PB20 */ {0, 0, 0, 0, 0, 0},
-	 /* PB19 */ {0, 0, 0, 0, 0, 0},
-	 /* PB18 */ {0, 0, 0, 0, 0, 0},
-	 /* PB17 */ {0, 0, 0, 0, 0, 0},
-	 /* PB16 */ {0, 0, 0, 0, 0, 0},
-	 /* PB15 */ {0, 0, 0, 0, 0, 0},
-	 /* PB14 */ {0, 0, 0, 0, 0, 0},
-	 /* PB13 */ {0, 0, 0, 0, 0, 0},
-	 /* PB12 */ {0, 0, 0, 0, 0, 0},
-	 /* PB11 */ {0, 0, 0, 0, 0, 0},
-	 /* PB10 */ {0, 0, 0, 0, 0, 0},
-	 /* PB9  */ {0, 0, 0, 0, 0, 0},
-	 /* PB8  */ {0, 0, 0, 0, 0, 0},
-	 /* PB7  */ {0, 0, 0, 0, 0, 0},
-	 /* PB6  */ {0, 0, 0, 0, 0, 0},
-	 /* PB5  */ {0, 0, 0, 0, 0, 0},
-	 /* PB4  */ {0, 0, 0, 0, 0, 0},
-					/* PB3  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PB2  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PB1  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PB0  */ {0, 0, 0, 0, 0, 0}
-					/* pin doesn't exist */
-	 },
-
-
-	{			/*            conf ppar psor pdir podr pdat */
-	 /* PC31 */ {0, 0, 0, 0, 0, 0},
-	 /* PC30 */ {0, 0, 0, 0, 0, 0},
-	 /* PC29 */ {0, 0, 0, 0, 0, 0},
-	 /* PC28 */ {0, 0, 0, 0, 0, 0},
-	 /* PC27 */ {0, 0, 0, 0, 0, 0},
-	 /* PC26 */ {0, 0, 0, 0, 0, 0},
-	 /* PC25 */ {0, 0, 0, 0, 0, 0},
-	 /* PC24 */ {0, 0, 0, 0, 0, 0},
-	 /* PC23 */ {0, 0, 0, 0, 0, 0},
-	 /* PC22 */ {0, 0, 0, 0, 0, 0},
-	 /* PC21 */ {0, 0, 0, 0, 0, 0},
-	 /* PC20 */ {0, 0, 0, 0, 0, 0},
-	 /* PC19 */ {0, 0, 0, 0, 0, 0},
-	 /* PC18 */ {0, 0, 0, 0, 0, 0},
-	 /* PC17 */ {0, 0, 0, 0, 0, 0},
-	 /* PC16 */ {0, 0, 0, 0, 0, 0},
-	 /* PC15 */ {0, 0, 0, 0, 0, 0},
-	 /* PC14 */ {0, 0, 0, 0, 0, 0},
-	 /* PC13 */ {0, 0, 0, 0, 0, 0},
-	 /* PC12 */ {0, 0, 0, 0, 0, 0},
-	 /* PC11 */ {0, 0, 0, 0, 0, 0},
-	 /* PC10 */ {0, 0, 0, 0, 0, 0},
-	 /* PC9  */ {0, 0, 0, 0, 0, 0},
-	 /* PC8  */ {0, 0, 0, 0, 0, 0},
-	 /* PC7  */ {0, 0, 0, 0, 0, 0},
-	 /* PC6  */ {0, 0, 0, 0, 0, 0},
-	 /* PC5  */ {0, 0, 0, 0, 0, 0},
-	 /* PC4  */ {0, 0, 0, 0, 0, 0},
-	 /* PC3  */ {0, 0, 0, 0, 0, 0},
-	 /* PC2  */ {0, 0, 0, 0, 0, 0},
-	 /* PC1  */ {0, 0, 0, 0, 0, 0},
-	 /* PC0  */ {0, 0, 0, 0, 0, 0}
-	 },
-
-
-	{			/*            conf ppar psor pdir podr pdat */
-	 /* PD31 */ {0, 0, 0, 0, 0, 0},
-	 /* PD30 */ {0, 0, 0, 0, 0, 0},
-	 /* PD29 */ {0, 0, 0, 0, 0, 0},
-	 /* PD28 */ {0, 0, 0, 0, 0, 0},
-	 /* PD27 */ {0, 0, 0, 0, 0, 0},
-	 /* PD26 */ {0, 0, 0, 0, 0, 0},
-	 /* PD25 */ {0, 0, 0, 0, 0, 0},
-	 /* PD24 */ {0, 0, 0, 0, 0, 0},
-	 /* PD23 */ {0, 0, 0, 0, 0, 0},
-	 /* PD22 */ {0, 0, 0, 0, 0, 0},
-	 /* PD21 */ {0, 0, 0, 0, 0, 0},
-	 /* PD20 */ {0, 0, 0, 0, 0, 0},
-	 /* PD19 */ {0, 0, 0, 0, 0, 0},
-	 /* PD18 */ {0, 0, 0, 0, 0, 0},
-	 /* PD17 */ {0, 0, 0, 0, 0, 0},
-	 /* PD16 */ {0, 0, 0, 0, 0, 0},
-					/* PD15 */ {1, 1, 1, 0, 0, 0},
-					/* I2C SDA */
-					/* PD14 */ {1, 1, 1, 0, 0, 0},
-					/* I2C SCL */
-	 /* PD13 */ {0, 0, 0, 0, 0, 0},
-	 /* PD12 */ {0, 0, 0, 0, 0, 0},
-	 /* PD11 */ {0, 0, 0, 0, 0, 0},
-	 /* PD10 */ {0, 0, 0, 0, 0, 0},
-					/* PD9  */ {1, 1, 0, 1, 0, 0},
-					/* SMC1 TXD */
-					/* PD8  */ {1, 1, 0, 0, 0, 0},
-					/* SMC1 RXD */
-	 /* PD7  */ {0, 0, 0, 0, 0, 0},
-	 /* PD6  */ {0, 0, 0, 0, 0, 0},
-	 /* PD5  */ {0, 0, 0, 0, 0, 0},
-	 /* PD4  */ {0, 0, 0, 0, 0, 0},
-					/* PD3  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PD2  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PD1  */ {0, 0, 0, 0, 0, 0},
-					/* pin doesn't exist */
-					/* PD0  */ {0, 0, 0, 0, 0, 0}
-					/* pin doesn't exist */
-	 }
-};
-
-#endif /* CONFIG_MPC8260 */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
-	      COGENT_CPU_MODULE " CPU Module\n");
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations while still
- * running in flash
- */
-
-int misc_init_f (void)
-{
-	printf ("DIPSW: ");
-	dipsw_init ();
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-#ifdef CONFIG_CMA111
-	return (32L * 1024L * 1024L);
-#else
-	unsigned char dipsw_val;
-	int dual, size0, size1;
-	long int memsize;
-
-	dipsw_val = dipsw_cooked ();
-
-	dual = dipsw_val & 0x01;
-	size0 = (dipsw_val & 0x08) >> 3;
-	size1 = (dipsw_val & 0x04) >> 2;
-
-	if (size0)
-		if (size1)
-			memsize = 16L * 1024L * 1024L;
-		else
-			memsize = 1L * 1024L * 1024L;
-	else if (size1)
-		memsize = 4L * 1024L * 1024L;
-	else {
-		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
-		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
-	}
-
-	if (dual)
-		memsize *= 2L;
-
-	return (memsize);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Miscelaneous platform dependent initialisations after monitor
- * has been relocated into ram
- */
-
-int misc_init_r (void)
-{
-	printf ("LCD:   ");
-	lcd_init ();
-
-#if 0
-	printf ("RTC:   ");
-	rtc_init ();
-
-	printf ("PAR:   ");
-	par_init ();
-
-	printf ("KBM:   ");
-	kbm_init ();
-
-	printf ("PCI:   ");
-	pci_init ();
-#endif
-	return (0);
-}

board/cogent/mb.h

@@ -1,513 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * defines for Cogent Motherboards
- */
-
-#ifndef _COGENT_MB_H
-#define _COGENT_MB_H
-
-/*
- * Cogent Motherboard Address Map
- *
- * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
- *
- * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
- * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
- * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
- * Most other motherboard devices have registers mapped into the area
- * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
- * is free for whatever.
- *
- * The location of the motherboard address space in the physical address space
- * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
- * module plugged into the motherboard and is configured above.
- *
- * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
- * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
- * 8 bit, or 1 byte, transfers can take place, so all the registers are
- * only 8 bits wide. The exceptions are the motherboard flash, which uses
- * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
- *
- * I/O registers within the mapped motherboard devices are 64 bit aligned
- * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
- * will be at byte 7 (the address + 7). For little endian addressing, the
- * register will be at byte 0 (the address + 0). To learn the endianess
- * we must include <endian.h>
- *
- * Take the CMA102 and CMA111 motherboards as examples...
- *
- * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
- * CMABus slots are each mapped directly onto the three general I/O slots.
- *
- * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
- * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
- * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
- * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
- * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
- * 0xA000000-0xDFFFFFF.
- */
-
-#define CMA_MB_RAM_BASE		(CONFIG_SYS_CMA_MB_BASE+0x0000000)
-#define CMA_MB_RAM_SIZE		0x2000000	/* dip sws set actual size */
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
-#define CMA_MB_SLOT1_BASE	(CONFIG_SYS_CMA_MB_BASE+0x2000000)
-#define CMA_MB_SLOT1_SIZE	0x2000000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
-#define CMA_MB_SLOT2_SIZE	0x2000000
-#endif
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_STDPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
-#define CMA_MB_STDPCI_SIZE	0x1ff0000
-#define CMA_MB_V360EPC_BASE	(CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
-#define CMA_MB_V360EPC_SIZE	0x10000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3_BASE	(CONFIG_SYS_CMA_MB_BASE+0x6000000)
-#define CMA_MB_SLOT3_SIZE	0x2000000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
-#define CMA_MB_EXTPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0xa000000)
-#define CMA_MB_EXTPCI_SIZE	0x4000000
-#endif
-
-#define CMA_MB_ROMLOW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
-#define CMA_MB_ROMLOW_SIZE	0x800000
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLLOW_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
-#define CMA_MB_FLLOW_EXEC_SIZE	0x100000
-#define CMA_MB_FLLOW_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe400000)
-#define CMA_MB_FLLOW_RDWR_SIZE	0x400000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-#define CMA_MB_RTC_BASE		(CONFIG_SYS_CMA_MB_BASE+0xe800000)
-#define CMA_MB_RTC_SIZE		0x4000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#define CMA_MB_SERPAR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900000)
-#define   CMA_MB_SERIALB_BASE	  (CMA_MB_SERPAR_BASE+0x00)
-#define   CMA_MB_SERIALA_BASE	  (CMA_MB_SERPAR_BASE+0x40)
-#define   CMA_MB_PARALLEL_BASE	  (CMA_MB_SERPAR_BASE+0x80)
-#define CMA_MB_SERPAR_SIZE	0xa0
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
-#define CMA_MB_PKBM_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900100)
-#define CMA_MB_PKBM_SIZE	0x10
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-#define CMA_MB_LCD_BASE		(CONFIG_SYS_CMA_MB_BASE+0xeb00000)
-#define CMA_MB_LCD_SIZE		0x10
-#endif
-
-#define CMA_MB_DIPSW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xec00000)
-#define CMA_MB_DIPSW_SIZE	0x10
-
-#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
-#define CMA_MB_SLOT1CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf100000)
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define   CMA_MB_SER2_BASE	  (CMA_MB_SLOT1CFG_BASE+0x80)
-#define     CMA_MB_SER2B_BASE	    (CMA_MB_SER2_BASE+0x00)
-#define     CMA_MB_SER2A_BASE	    (CMA_MB_SER2_BASE+0x40)
-#endif
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
-#define   CMA_MB_S1KBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
-#endif
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
-#define   CMA_MB_IREQ1STAT_BASE	  (CMA_MB_SLOT1CFG_BASE+0x100)
-#define   CMA_MB_AKBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
-#define   CMA_MB_IREQ1MASK_BASE	  (CMA_MB_SLOT1CFG_BASE+0x300)
-#endif
-#define CMA_MB_SLOT1CFG_SIZE	0x400
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
-#define   CMA_MB_S2KBM_BASE	  (CMA_MB_SLOT2CFG_BASE+0x200)
-#endif
-#define CMA_MB_SLOT2CFG_SIZE	0x400
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_PCICTL_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
-#define   CMA_MB_PCI_V3CTL_BASE	  (CMA_MB_PCICTL_BASE+0x100)
-#define   CMA_MB_PCI_IDSEL_BASE	  (CMA_MB_PCICTL_BASE+0x200)
-#define   CMA_MB_PCI_IMASK_BASE	  (CMA_MB_PCICTL_BASE+0x300)
-#define   CMA_MB_PCI_ISTAT_BASE	  (CMA_MB_PCICTL_BASE+0x400)
-#define   CMA_MB_PCI_MBID_BASE	  (CMA_MB_PCICTL_BASE+0x500)
-#define   CMA_MB_PCI_MBREV_BASE	  (CMA_MB_PCICTL_BASE+0x600)
-#define CMA_MB_PCICTL_SIZE	0x700
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf300000)
-#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
-#define   CMA_MB_S3KBM_BASE	  (CMA_MB_SLOT3CFG_BASE+0x200)
-#endif
-#define CMA_MB_SLOT3CFG_SIZE	0x400
-#endif
-
-#define CMA_MB_ROMHIGH_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
-#define CMA_MB_ROMHIGH_SIZE	0x800000
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLHIGH_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
-#define CMA_MB_FLHIGH_EXEC_SIZE	0x100000
-#define CMA_MB_FLHIGH_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xfc00000)
-#define CMA_MB_FLHIGH_RDWR_SIZE	0x400000
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-
-/* PCI Control Register bits */
-
-/* V360EPC Control register bits */
-#define CMA_MB_PCI_V3CTL_RESET	0x01
-#define CMA_MB_PCI_V3CTL_EXTADD	0x08
-
-/* PCI ID Select register bits */
-#define CMA_MB_PCI_IDSEL_SLOTA	0x01
-#define CMA_MB_PCI_IDSEL_SLOTB	0x02
-#define CMA_MB_PCI_IDSEL_GD82559 0x04
-#define CMA_MB_PCI_IDSEL_B69000	0x08
-#define CMA_MB_PCI_IDSEL_PD6832	0x10
-
-/* PCI Interrupt Mask/Status register bits */
-#define CMA_MB_PCI_IMS_INTA	0x01
-#define CMA_MB_PCI_IMS_INTB	0x02
-#define CMA_MB_PCI_IMS_INTC	0x04
-#define CMA_MB_PCI_IMS_INTD	0x08
-#define CMA_MB_PCI_IMS_CBINT	0x10
-#define CMA_MB_PCI_IMS_V3LINT	0x80
-
-#endif
-
-#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
-
-/*
- * IREQ1 Interrupt Mask/Status register bits
- * (Note: not available on CMA150 - must poll HT6542B interrupt register)
- */
-
-#define IREQ1_MINT	0x01
-#define IREQ1_KINT	0x02
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define IREQ1_SINT2	0x04
-#define IREQ1_SINT3	0x08
-#endif
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef USE_HOSTCC
-#include <endian.h>		/* avoid using private kernel header files */
-#else
-#include <asm/byteorder.h>	/* use U-Boot provided headers */
-#endif
-
-/* a single CMA10x motherboard i/o register */
-typedef
-    struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-	unsigned char value;
-#endif
-	unsigned char filler[7];
-#if __BYTE_ORDER == __BIG_ENDIAN
-	unsigned char value;
-#endif
-    }
-cma_mb_reg;
-
-extern __inline__ unsigned char
-cma_mb_reg_read(volatile cma_mb_reg *reg)
-{
-    unsigned char data = reg->value;
-    __asm__ __volatile__ ("eieio" : : : "memory");
-    return data;
-}
-
-extern __inline__ void
-cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
-{
-    reg->value = data;
-    __asm__ __volatile__ ("eieio" : : : "memory");
-}
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-
-/* MK48T02 RTC registers */
-typedef
-    struct {
-	cma_mb_reg sram[2040];/* Battery-Backed SRAM */
-	cma_mb_reg clk_ctl;	/* Clock Control Register */
-	cma_mb_reg clk_sec;	/* Clock Seconds Register */
-	cma_mb_reg clk_min;	/* Clock Minutes Register */
-	cma_mb_reg clk_hour;	/* Clock Hour Register */
-	cma_mb_reg clk_day;	/* Clock Day Register */
-	cma_mb_reg clk_date;	/* Clock Date Register */
-	cma_mb_reg clk_month;	/* Clock Month Register */
-	cma_mb_reg clk_year;	/* Clock Year Register */
-    }
-cma_mb_rtc;
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-
-/* ST16C522 Serial I/O */
-typedef
-    struct {
-	cma_mb_reg ser_rhr;	/* Receive Holding Register (R, DLAB=0) */
-	cma_mb_reg ser_ier;	/* Interrupt Enable Register (R/W, DLAB=0) */
-	cma_mb_reg ser_isr;	/* Interrupt Status Register (R) */
-	cma_mb_reg ser_lcr;	/* Line Control Register (R/W) */
-	cma_mb_reg ser_mcr;	/* Modem Control Register (R/W) */
-	cma_mb_reg ser_lsr;	/* Line Status Register (R) */
-	cma_mb_reg ser_msr;	/* Modem Status Register (R/W) */
-	cma_mb_reg ser_spr;	/* Scratch Pad Register (R/W) */
-    }
-cma_mb_serial;
-
-#define ser_thr	ser_rhr		/* Transmit Holding Register (W, DLAB=0) */
-#define ser_brl	ser_rhr		/* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
-#define ser_brh	ser_ier		/* Baud Rate Divisor High Byte (R/W, DLAB=1) */
-#define ser_fcr	ser_isr		/* FIFO Control Register (W) */
-#define ser_nop	ser_lsr		/* No Operation (W) */
-
-/* ST16C522 Parallel I/O */
-typedef
-    struct {
-	cma_mb_reg par_rdr;	/* Port Read Data Register (R) */
-	cma_mb_reg par_sr;	/* Status Register (R) */
-	cma_mb_reg par_cmd;	/* Command Register (R) */
-    }
-cma_mb_parallel;
-
-#define par_wdr	par_rdr		/* Port Write Data Register (W) */
-#define par_ios	par_sr		/* I/O Select Register (W) */
-#define par_ctl	par_cmd		/* Control Register (W) */
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
-
-/* HT6542B PS/2 Keyboard/Mouse Controller */
-typedef
-    struct {
-	cma_mb_reg kbm_rdr;	/* Read Data Register (R) */
-	cma_mb_reg kbm_sr;	/* Status Register (R) */
-    }
-cma_mb_kbm;
-
-#define kbm_wdr	kbm_rdr		/* Write Data Register (W) */
-#define kbm_cmd	kbm_sr		/* Command Register (W) */
-
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-
-/* HD44780 LCD Display */
-typedef
-    struct {
-	cma_mb_reg lcd_ccr;	/* Current Character Register (R/W) */
-	cma_mb_reg lcd_bsr;	/* Busy Status Register (R) */
-    }
-cma_mb_lcd;
-
-#define lcd_cmd	lcd_bsr		/* Command Register (W) */
-
-#endif
-
-/* 8-Position Configuration Switch */
-typedef
-    struct {
-	cma_mb_reg dip_val;	/* Dip Switch value (R) */
-    }
-cma_mb_dipsw;
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-
-/* V360EPC PCI Bridge */
-typedef
-    struct {
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-	unsigned short v3_pci_vendor;		/* 0x00 */
-	unsigned short v3_pci_device;
-	unsigned short v3_pci_cmd;		/* 0x04 */
-	unsigned short v3_pci_stat;
-	unsigned long  v3_pci_cc_rev;		/* 0x08 */
-	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
-	unsigned long  v3_pci_io_base;		/* 0x10 */
-	unsigned long  v3_pci_base0;		/* 0x14 */
-	unsigned long  v3_pci_base1;		/* 0x18 */
-	unsigned long  reserved1[4];		/* 0x1c */
-	unsigned short v3_pci_sub_vendor;	/* 0x2c */
-	unsigned short v3_pci_sub_id;
-	unsigned long  v3_pci_rom;		/* 0x30 */
-	unsigned long  reserved2[2];		/* 0x34 */
-	unsigned long  v3_pci_bparam;		/* 0x3c */
-	unsigned long  v3_pci_map0;		/* 0x40 */
-	unsigned long  v3_pci_map1;		/* 0x44 */
-	unsigned long  v3_pci_int_stat;		/* 0x48 */
-	unsigned long  v3_pci_int_cfg;		/* 0x4c */
-	unsigned long  reserved3[1];		/* 0x50 */
-	unsigned long  v3_lb_base0;		/* 0x54 */
-	unsigned long  v3_lb_base1;		/* 0x58 */
-	unsigned short reserved4;		/* 0x5c */
-	unsigned short v3_lb_map0;
-	unsigned short reserved5;		/* 0x60 */
-	unsigned short v3_lb_map1;
-	unsigned short v3_lb_base2;		/* 0x64 */
-	unsigned short v3_lb_map2;
-	unsigned long  v3_lb_size;		/* 0x68 */
-	unsigned short reserved6;		/* 0x6c */
-	unsigned short v3_lb_io_base;
-	unsigned short v3_fifo_cfg;		/* 0x70 */
-	unsigned short v3_fifo_priority;
-	unsigned short v3_fifo_stat;		/* 0x74 */
-	unsigned char  v3_lb_istat;
-	unsigned char  v3_lb_imask;
-	unsigned short v3_system;		/* 0x78 */
-	unsigned short v3_lb_cfg;
-	unsigned short v3_pci_cfg;		/* 0x7c */
-	unsigned short reserved7;
-	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
-	unsigned long  v3_dma_local_addr0;	/* 0x84 */
-	unsigned long  v3_dma_length0:24;	/* 0x88 */
-	unsigned long  v3_dma_csr0:8;
-	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
-	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
-	unsigned long  v3_dma_local_addr1;	/* 0x94 */
-	unsigned long  v3_dma_length1:24;	/* 0x98 */
-	unsigned long  v3_dma_csr1:8;
-	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
-	unsigned long  v3_i20_mups[8];		/* 0xa0 */
-	unsigned char  v3_mail_data0;		/* 0xc0 */
-	unsigned char  v3_mail_data1;
-	unsigned char  v3_mail_data2;
-	unsigned char  v3_mail_data3;
-	unsigned char  v3_mail_data4;		/* 0xc4 */
-	unsigned char  v3_mail_data5;
-	unsigned char  v3_mail_data6;
-	unsigned char  v3_mail_data7;
-	unsigned char  v3_mail_data8;		/* 0xc8 */
-	unsigned char  v3_mail_data9;
-	unsigned char  v3_mail_data10;
-	unsigned char  v3_mail_data11;
-	unsigned char  v3_mail_data12;		/* 0xcc */
-	unsigned char  v3_mail_data13;
-	unsigned char  v3_mail_data14;
-	unsigned char  v3_mail_data15;
-	unsigned short v3_pci_mail_iewr;	/* 0xd0 */
-	unsigned short v3_pci_mail_ierd;
-	unsigned short v3_lb_mail_iewr;		/* 0xd4 */
-	unsigned short v3_lb_mail_ierd;
-	unsigned short v3_mail_wr_stat;		/* 0xd8 */
-	unsigned short v3_mail_rd_stat;
-	unsigned long  v3_qba_map;		/* 0xdc */
-	unsigned long  v3_dma_delay:8;		/* 0xe0 */
-	unsigned long  reserved8:24;
-	unsigned long  reserved9[7];		/* 0xe4 */
-#endif
-#if __BYTE_ORDER == __BIG_ENDIAN
-	unsigned short v3_pci_device;		/* 0x00 */
-	unsigned short v3_pci_vendor;
-	unsigned short v3_pci_stat;		/* 0x04 */
-	unsigned short v3_pci_cmd;
-	unsigned long  v3_pci_cc_rev;		/* 0x08 */
-	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
-	unsigned long  v3_pci_io_base;		/* 0x10 */
-	unsigned long  v3_pci_base0;		/* 0x14 */
-	unsigned long  v3_pci_base1;		/* 0x18 */
-	unsigned long  reserved1[4];		/* 0x1c */
-	unsigned short v3_pci_sub_id;		/* 0x2c */
-	unsigned short v3_pci_sub_vendor;
-	unsigned long  v3_pci_rom;		/* 0x30 */
-	unsigned long  reserved2[2];		/* 0x34 */
-	unsigned long  v3_pci_bparam;		/* 0x3c */
-	unsigned long  v3_pci_map0;		/* 0x40 */
-	unsigned long  v3_pci_map1;		/* 0x44 */
-	unsigned long  v3_pci_int_stat;		/* 0x48 */
-	unsigned long  v3_pci_int_cfg;		/* 0x4c */
-	unsigned long  reserved3;		/* 0x50 */
-	unsigned long  v3_lb_base0;		/* 0x54 */
-	unsigned long  v3_lb_base1;		/* 0x58 */
-	unsigned short v3_lb_map0;		/* 0x5c */
-	unsigned short reserved4;
-	unsigned short v3_lb_map1;		/* 0x60 */
-	unsigned short reserved5;
-	unsigned short v3_lb_map2;		/* 0x64 */
-	unsigned short v3_lb_base2;
-	unsigned long  v3_lb_size;		/* 0x68 */
-	unsigned short v3_lb_io_base;		/* 0x6c */
-	unsigned short reserved6;
-	unsigned short v3_fifo_priority;	/* 0x70 */
-	unsigned short v3_fifo_cfg;
-	unsigned char  v3_lb_imask;		/* 0x74 */
-	unsigned char  v3_lb_istat;
-	unsigned short v3_fifo_stat;
-	unsigned short v3_lb_cfg;		/* 0x78 */
-	unsigned short v3_system;
-	unsigned short reserved7;		/* 0x7c */
-	unsigned short v3_pci_cfg;
-	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
-	unsigned long  v3_dma_local_addr0;	/* 0x84 */
-	unsigned long  v3_dma_csr0:8;		/* 0x88 */
-	unsigned long  v3_dma_length0:24;
-	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
-	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
-	unsigned long  v3_dma_local_addr1;	/* 0x94 */
-	unsigned long  v3_dma_csr1:8;		/* 0x98 */
-	unsigned long  v3_dma_length1:24;
-	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
-	unsigned long  v3_i20_mups[8];		/* 0xa0 */
-	unsigned char  v3_mail_data3;		/* 0xc0 */
-	unsigned char  v3_mail_data2;
-	unsigned char  v3_mail_data1;
-	unsigned char  v3_mail_data0;
-	unsigned char  v3_mail_data7;		/* 0xc4 */
-	unsigned char  v3_mail_data6;
-	unsigned char  v3_mail_data5;
-	unsigned char  v3_mail_data4;
-	unsigned char  v3_mail_data11;		/* 0xc8 */
-	unsigned char  v3_mail_data10;
-	unsigned char  v3_mail_data9;
-	unsigned char  v3_mail_data8;
-	unsigned char  v3_mail_data15;		/* 0xcc */
-	unsigned char  v3_mail_data14;
-	unsigned char  v3_mail_data13;
-	unsigned char  v3_mail_data12;
-	unsigned short v3_pci_mail_ierd;	/* 0xd0 */
-	unsigned short v3_pci_mail_iewr;
-	unsigned short v3_lb_mail_ierd;		/* 0xd4 */
-	unsigned short v3_lb_mail_iewr;
-	unsigned short v3_mail_rd_stat;		/* 0xd8 */
-	unsigned short v3_mail_wr_stat;
-	unsigned long  v3_qba_map;		/* 0xdc */
-	unsigned long  reserved8:24;		/* 0xe0 */
-	unsigned long  v3_dma_delay:8;
-	unsigned long  reserved9[7];		/* 0xe4 */
-#endif
-    }						/* 0x100 */
-cma_mb_v360epc;
-
-#endif
-
-#endif	/* __ASSEMBLY__ */
-
-#endif	/* _COGENT_MB_H */

board/cogent/par.c

@@ -1,3 +0,0 @@
-/* parallel not implemented yet */
-
-int cma_parallel_not_implemented = 1;

board/cogent/par.h

@@ -1,3 +0,0 @@
-/* parallel not implemented yet */
-
-extern int cma_parallel_not_implemented;

board/cogent/pci.c

@@ -1,3 +0,0 @@
-/* pci not implemented yet */
-
-int cma_pci_not_implemented = 1;

board/cogent/pci.h

@@ -1,3 +0,0 @@
-/* pci not implemented yet */
-
-extern int cma_pci_not_implemented;

board/cogent/rtc.c

@@ -1,3 +0,0 @@
-/* rtc not implemented yet */
-
-int cma_rtc_not_implemented = 1;

board/cogent/rtc.h

@@ -1,3 +0,0 @@
-/* rtc not implemented yet */
-
-extern int cma_rtc_not_implemented;

board/cogent/serial.c

@@ -1,189 +0,0 @@
-/*
- * Simple serial driver for Cogent motherboard serial ports
- * for use during boot
- */
-
-#include <common.h>
-#include "serial.h"
-#include <serial.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-
-#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
-	(defined(CONFIG_MPC8260) && defined(CONFIG_CONS_NONE))
-
-#if CONFIG_CONS_INDEX == 1
-#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALA_BASE
-#elif CONFIG_CONS_INDEX == 2
-#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALB_BASE
-#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_SERIAL_BASE	CMA_MB_SER2A_BASE
-#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_SERIAL_BASE	CMA_MB_SER2B_BASE
-#else
-#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
-#endif
-
-static int cogent_serial_init(void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
-	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
-	serial_setbrg ();
-	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
-	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
-	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
-
-	return (0);
-}
-
-static void cogent_serial_setbrg(void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-	unsigned int divisor;
-	unsigned char lcr;
-
-	if ((divisor = br_to_div (gd->baudrate)) == 0)
-		divisor = DEFDIV;
-
-	lcr = cma_mb_reg_read (&mbsp->ser_lcr);
-	cma_mb_reg_write (&mbsp->ser_lcr, lcr | 0x80);	/* Access baud rate(set DLAB) */
-	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
-	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
-	cma_mb_reg_write (&mbsp->ser_lcr, lcr);	/* unset DLAB */
-}
-
-static void cogent_serial_putc(const char c)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
-	if (c == '\n')
-		serial_putc ('\r');
-
-	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
-
-	cma_mb_reg_write (&mbsp->ser_thr, c);
-}
-
-static int cogent_serial_getc(void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
-	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
-
-	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
-}
-
-static int cogent_serial_tstc(void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
-
-	return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
-}
-
-static struct serial_device cogent_serial_drv = {
-	.name	= "cogent_serial",
-	.start	= cogent_serial_init,
-	.stop	= NULL,
-	.setbrg	= cogent_serial_setbrg,
-	.putc	= cogent_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= cogent_serial_getc,
-	.tstc	= cogent_serial_tstc,
-};
-
-void cogent_serial_initialize(void)
-{
-	serial_register(&cogent_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &cogent_serial_drv;
-}
-#endif /* CONS_NONE */
-
-#if defined(CONFIG_CMD_KGDB) && \
-    defined(CONFIG_KGDB_NONE)
-
-#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
-#error Console and kgdb are on the same serial port - this is not supported
-#endif
-
-#if CONFIG_KGDB_INDEX == 1
-#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALA_BASE
-#elif CONFIG_KGDB_INDEX == 2
-#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALB_BASE
-#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2A_BASE
-#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
-#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2B_BASE
-#else
-#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
-#endif
-
-void kgdb_serial_init (void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-	unsigned int divisor;
-
-	if ((divisor = br_to_div (CONFIG_KGDB_BAUDRATE)) == 0)
-		divisor = DEFDIV;
-
-	cma_mb_reg_write (&mbsp->ser_ier, 0x00);	/* turn off interrupts */
-	cma_mb_reg_write (&mbsp->ser_lcr, 0x80);	/* Access baud rate(set DLAB) */
-	cma_mb_reg_write (&mbsp->ser_brl, divisor & 0xff);
-	cma_mb_reg_write (&mbsp->ser_brh, (divisor >> 8) & 0xff);
-	cma_mb_reg_write (&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
-	cma_mb_reg_write (&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
-	cma_mb_reg_write (&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
-
-	printf ("[on cma10x serial port B] ");
-}
-
-void putDebugChar (int c)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
-	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_THRE) == 0);
-
-	cma_mb_reg_write (&mbsp->ser_thr, c & 0xff);
-}
-
-void putDebugStr (const char *str)
-{
-	while (*str != '\0') {
-		if (*str == '\n')
-			putDebugChar ('\r');
-		putDebugChar (*str++);
-	}
-}
-
-int getDebugChar (void)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
-	while ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) == 0);
-
-	return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
-}
-
-void kgdb_interruptible (int yes)
-{
-	cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_KGDB_SER_BASE;
-
-	if (yes == 1) {
-		printf ("kgdb: turning serial ints on\n");
-		cma_mb_reg_write (&mbsp->ser_ier, 0xf);
-	} else {
-		printf ("kgdb: turning serial ints off\n");
-		cma_mb_reg_write (&mbsp->ser_ier, 0x0);
-	}
-}
-
-#endif /* KGDB && KGDB_NONE */
-
-#endif /* CAPS & SERPAR */

board/cogent/serial.h

@@ -1,15 +0,0 @@
-/* Line Status Register bits */
-#define LSR_DR		0x01	/* Data ready */
-#define LSR_OE		0x02	/* Overrun */
-#define LSR_PE		0x04	/* Parity error */
-#define LSR_FE		0x08	/* Framing error */
-#define LSR_BI		0x10	/* Break */
-#define LSR_THRE	0x20	/* Xmit holding register empty */
-#define LSR_TEMT	0x40	/* Xmitter empty */
-#define LSR_ERR		0x80	/* Error */
-
-#define CLKRATE		3686400	/* cogent motherboard serial clk = 3.6864MHz */
-#define DEFDIV		1	/* default to 230400 bps */
-
-#define br_to_div(br)	(CLKRATE / (16 * (br)))
-#define div_to_br(div)	(CLKRATE / (16 * (div)))

board/cogent/u-boot.lds

@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-#ifdef CONFIG_MPC8260
-    arch/powerpc/cpu/mpc8260/start.o	(.text*)
-#else
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-#endif
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}

board/cogent/u-boot.lds.debug

@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}

configs/cogent_mpc8260_defconfig

@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC8260=y
-CONFIG_TARGET_COGENT_MPC8260=y

configs/cogent_mpc8xx_defconfig

@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_COGENT_MPC8XX=y

doc/README.scrapyard

@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+cogent_mpc8260   powerpc     mpc8260        -           -           Murray Jensen <Murray.Jensen@csiro.au>
+cogent_8xx       powerpc     mpc8xx         -           -           Murray Jensen <Murray.Jensen@csiro.au>
 ESTEEM192E       powerpc     mpc8xx         -           -           Conn Clark <clark@esteem.com>
 IP860            powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>
 IVML24           powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>

include/configs/cogent_common.h

@@ -1,192 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen, CSIRO-MST
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CONFIG_COGENT_COMMON_H
-#define _CONFIG_COGENT_COMMON_H
-
-/*
- * Cogent Motherboard Capabilities
- */
-#define CMA_MB_CAP_SERPAR	0x0001	/* has dual serial+parallel (16C552) */
-#define CMA_MB_CAP_LCD		0x0002	/* has LCD display (HD44780) */
-#define CMA_MB_CAP_FLASH	0x0004	/* has flash (E28F800B or AM29F800BB) */
-#define CMA_MB_CAP_RTC		0x0008	/* has RTC+NVRAM (MK48T02) */
-#define CMA_MB_CAP_ETHER	0x0010	/* has Ethernet (MB86964) */
-#define CMA_MB_CAP_SLOT1	0x0020	/* has CMABus slot 1 */
-#define CMA_MB_CAP_SLOT2	0x0040	/* has CMABus slot 2 */
-#define CMA_MB_CAP_SLOT3	0x0080	/* has CMABus slot 3 */
-#define CMA_MB_CAP_KBM		0x0100	/* has PS/2 keyboard+mouse (HT6542B) */
-#define CMA_MB_CAP_SER2		0x0200	/* has 2nd dual serial (16C2552) */
-#define CMA_MB_CAP_PCI		0x0400	/* has pci bridge (V360EPC) */
-#define CMA_MB_CAP_PCI_EXT	0x0800	/* can access extended pci space  */
-#define CMA_MB_CAP_PCI_ETHER	0x1000	/* has 10/100 ether on PCI (GD82559) */
-#define CMA_MB_CAP_PCI_VIDEO	0x2000	/* has video int'face on PCI (B69000) */
-#define CMA_MB_CAP_PCI_CARDBUS	0x4000	/* has Cardbus Ctlr on PCI (PD6832) */
-
-/*
- * Cogent option sanity checking
- */
-
-#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
-      defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
-
-/*
- * check a PowerPC 8xx cpu module has been selected
- */
-
-# if defined(CONFIG_CMA286_21)
-
-#  define COGENT_CPU_MODULE	"CMA286-21"
-
-# elif defined(CONFIG_CMA286_60_OLD)
-
-#  define COGENT_CPU_MODULE	"CMA286-60 (old)"
-
-# elif defined(CONFIG_CMA286_60)
-
-#  define COGENT_CPU_MODULE	"CMA286-60"
-
-# elif defined(CONFIG_CMA286_60P)
-
-#  define COGENT_CPU_MODULE	"CMA286-60P"
-
-# elif defined(CONFIG_CMA287_21)
-
-#  define COGENT_CPU_MODULE	"CMA287-21"
-
-# elif defined(CONFIG_CMA287_50)
-
-#  define COGENT_CPU_MODULE	"CMA287-50"
-
-# else
-
-#  error Cogent CPU Module must be a PowerPC MPC8xx module
-
-# endif
-
-#elif defined(CONFIG_MPC8260)
-
-/*
- * check a PowerPC 8260 cpu module has been selected
- */
-
-# if defined(CONFIG_CMA282)
-
-#  define COGENT_CPU_MODULE	"CMA282"
-
-# else
-
-#  error Cogent CPU Module must be a PowerPC MPC8260 module
-
-# endif
-
-#else
-
-# error CPU type must be PowerPC 8xx or 8260
-
-#endif
-
-/*
- * check a motherboard has been selected
- * define the motherboard capabilities while we're at it
- */
-
-#if defined(CONFIG_CMA101)
-
-# define COGENT_MOTHERBOARD	"CMA101"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
-				 CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS		3
-
-#elif defined(CONFIG_CMA102)
-
-# define COGENT_MOTHERBOARD	"CMA102"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
-				 CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
-# define CMA_MB_NSLOTS		3
-
-#elif defined(CONFIG_CMA110)
-
-# define COGENT_MOTHERBOARD	"CMA110"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
-# define CMA_MB_NSLOTS		0
-
-#elif defined(CONFIG_CMA111)
-
-# define COGENT_MOTHERBOARD	"CMA111"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
-				 CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
-				 CMA_MB_CAP_PCI_ETHER)
-# define CMA_MB_NSLOTS		1
-
-#elif defined(CONFIG_CMA120)
-
-# define COGENT_MOTHERBOARD	"CMA120"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
-				 CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
-				 CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
-				 CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
-# define CMA_MB_NSLOTS		1
-
-#elif defined(CONFIG_CMA150)
-
-# define COGENT_MOTHERBOARD	"CMA150"
-# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
-				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
-				 CMA_MB_CAP_KBM)
-# define CMA_MB_NSLOTS		0
-
-#else
-
-# error Cogent Motherboard either unsupported or undefined
-
-#endif
-
-/*
- * check a flash i/o module has been selected if no flash on m/b
- */
-
-#if defined(CONFIG_CMA302)
-
-# define COGENT_FLASH_MODULE	"CMA302"
-
-#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
-
-# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
-
-#endif
-
-/*
- * some further sanity checks
- */
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#error Cogent Sanity Check: Both Slot2 and PCI are defined
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Extended PCI capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#error Motherboard ethernet capability defined without PCI capability
-#endif
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#error 2nd dual serial capability defined without serial/parallel capability
-#endif
-#include "../board/cogent/mb.h"
-#endif	/* _CONFIG_COGENT_COMMON_H */

include/configs/cogent_mpc8260.h

@@ -1,392 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
-#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
-#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on something else*/
-#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
-#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
-#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
-#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
-#define	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
-
-/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
-#define CONFIG_8260_CLKIN	66666666	/* in Hz */
-
-#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
-#define CONFIG_BAUDRATE		230400
-#else
-#define CONFIG_BAUDRATE		9600
-#endif
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_KGDB
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#ifdef DEBUG
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
-#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
-#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
-#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
-# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
-# else
-#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
-# endif
-#endif
-
-#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#ifdef CONFIG_CONS_NONE
-#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
-#endif
-#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-#define CONFIG_SYS_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
-			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
-/* no slaves so just duplicate the master hrcw */
-#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
-#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
-#else
-#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
-#endif
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
-#else
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR		RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		BCR_EBM
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-			 SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-#if defined(CONFIG_CMA282)
-
-/*
- * Init Memory Controller:
- *
- * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
- * and CS2 for (optional) local bus RAM on the CPU module.
- *
- * Note the motherboard address space (256 Mbyte in size) is connected
- * to the 60x Bus and is located starting at address 0. The Hard Reset
- * Configuration Word should put the 60x Bus into External Bus Mode, since
- * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE	/* EPROM */
-#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
-#if 0
-#define CONFIG_SYS_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
-#define CONFIG_SYS_CMA_CS2_SIZE	(16 << 20)
-#endif
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom at any other addresses will disappear.
- */
-
-/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
-/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
-#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
-				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
-
-/*
- * CS2 enables the Local Bus SDRAM on the CPU Module
- *
- * Will leave this unset for the moment, because a) my CPU module has no
- * SDRAM installed (it is optional); and b) it will require programming
- * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
- * if you can't test it.
- */
-
-#if 0
-/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
-/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
-#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
-#endif
-
-#endif
-#endif	/* __CONFIG_H */

include/configs/cogent_mpc8xx.h

@@ -1,349 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Config header file for Cogent platform using an MPC8xx CPU module
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
-#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
-
-#define	CONFIG_SYS_TEXT_BASE	0xfff00000
-
-#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/
-
-/* Cogent Modular Architecture options */
-#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
-#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
-#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */
-
-/* serial console configuration */
-#undef	CONFIG_8xx_CONS_SMC1
-#undef	CONFIG_8xx_CONS_SMC2
-#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */
-
-#if defined(CONFIG_CMA286_60_OLD)
-#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
-#endif
-
-#define CONFIG_BAUDRATE		230400
-
-#define CONFIG_HARD_I2C		/* I2C with hardware support */
-#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
-#else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-#endif
-#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
-
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
-#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
-#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_ALLOC_DPRAM
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Low Level Cogent settings
- * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
- * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
- * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
- * (second 2 for CMA120 only)
- */
-#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
-
-#include <configs/cogent_common.h>
-
-#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
-#define CONFIG_SHOW_ACTIVITY
-#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-/*
- * flash exists on the motherboard
- * set these four according to TOP dipsw:
- * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
- * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
- */
-#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
-#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
-#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
-#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
-#endif
-#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
-#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
-#ifdef CONFIG_CMA302
-#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
-#else
-#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
-#endif
-#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
-#ifdef CONFIG_CMA302
-#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
-#else
-#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
-#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
-#endif
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control				11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit - leave PLL multiplication factor unchanged !
- */
-#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register		15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF11
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
-			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-			 SCCR_DFALCD00)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define	CONFIG_SYS_DER	0x2002000F*/
-#define CONFIG_SYS_DER	0
-
-#if defined(CONFIG_CMA286_60_OLD)
-
-/*
- * Init Memory Controller:
- *
- * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
- * they are actually the final settings for this cpu/board, because the
- * flash and RAM are on the motherboard, accessed via the CMAbus, and the
- * mappings are pretty much fixed.
- *
- * (the *_SIZE vars must be a power of 2)
- */
-
-#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE		/* EPROM */
-#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
-#define CONFIG_SYS_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
-#define CONFIG_SYS_CMA_CS1_SIZE	(64 << 20)
-#define CONFIG_SYS_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
-#define CONFIG_SYS_CMA_CS2_SIZE	(64 << 20)
-#define CONFIG_SYS_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
-#define CONFIG_SYS_CMA_CS3_SIZE	(32 << 20)
-
-/*
- * CS0 maps the EPROM on the cpu module
- * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
- *
- * Note: We must have already transferred control to the final location
- * of the EPROM before these are used, because when BR0/OR0 are set, the
- * mirror of the eprom at any other addresses will disappear.
- */
-
-/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
-/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
-#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
-
-/*
- * CS1 maps motherboard DRAM and motherboard I/O slot 1
- * (each 32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CONFIG_SYS_OR1_PRELIM	((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS2 maps motherboard I/O slots 2 and 3
- * (each 32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
-#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
-
-/*
- * CS3 maps motherboard I/O
- * (32Mbyte in size)
- */
-
-/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
-#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
-/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
-#define CONFIG_SYS_OR3_PRELIM	((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
-
-#endif
-#endif	/* __CONFIG_H */