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@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
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static int rockchip_spi_calc_modclk(ulong max_freq)
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{
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+ /*
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+ * While this is not strictly correct for the RK3368, as the
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+ * GPLL will be 576MHz, things will still work, as the
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+ * clk_set_rate(...) implementation in our clock-driver will
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+ * chose the next closest rate not exceeding what we request
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+ * based on the output of this function.
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+ */
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+
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unsigned div;
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const unsigned long gpll_hz = 594000000UL;
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@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
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static const struct udevice_id rockchip_spi_ids[] = {
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{ .compatible = "rockchip,rk3288-spi" },
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+ { .compatible = "rockchip,rk3368-spi" },
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{ .compatible = "rockchip,rk3399-spi" },
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{ }
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};
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