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@@ -68,6 +68,34 @@ static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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+static iomux_v3_cfg_t const usdhc2_pads[] = {
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+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const usdhc3_pads[] = {
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+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+
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+ /* CD pin */
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+ MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+
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+ /* RST_B, used for power reset cycle */
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+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@@ -249,23 +277,84 @@ int board_early_init_f(void)
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return 0;
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}
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-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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+ {USDHC2_BASE_ADDR, 0, 4},
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+ {USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
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+#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
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+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
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+
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int board_mmc_getcd(struct mmc *mmc)
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{
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- return 1; /* Assume boot SD always present */
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+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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+ int ret = 0;
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+
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+ switch (cfg->esdhc_base) {
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+ case USDHC2_BASE_ADDR:
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+ ret = 1; /* Assume uSDHC2 is always present */
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+ break;
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+ case USDHC3_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC3_CD_GPIO);
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+ break;
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+ case USDHC4_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC4_CD_GPIO);
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+ break;
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+ }
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+
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+ return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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- imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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+ int i, ret;
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- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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+ /*
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+ * According to the board_mmc_init() the following map is done:
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+ * (U-boot device node) (Physical Port)
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+ * mmc0 USDHC2
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+ * mmc1 USDHC3
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+ * mmc2 USDHC4
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+ */
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+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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+ switch (i) {
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+ case 0:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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+ break;
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+ case 1:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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+ gpio_direction_input(USDHC3_CD_GPIO);
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+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
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+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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+ break;
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+ case 2:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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+ gpio_direction_input(USDHC4_CD_GPIO);
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+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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+ break;
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+ default:
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+ printf("Warning: you configured more USDHC controllers"
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+ "(%d) than supported by the board\n", i + 1);
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+ return -EINVAL;
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+ }
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+
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+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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+ if (ret) {
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+ printf("Warning: failed to initialize mmc dev %d\n", i);
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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}
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+
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int board_init(void)
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{
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/* Address of boot parameters */
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