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@@ -67,23 +67,34 @@ __secure void imx_enable_cpu_ca7(int cpu, bool enable)
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writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
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}
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-__secure int imx_cpu_on(int fn, int cpu, int pc)
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+__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep,
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+ u32 context_id)
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{
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- writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
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+ u32 cpu = (mpidr & 0x1);
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+
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+ psci_save(cpu, ep, context_id);
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+
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+ writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
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imx_gpcv2_set_core1_power(true);
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imx_enable_cpu_ca7(cpu, true);
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return 0;
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}
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-__secure int imx_cpu_off(int cpu)
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+__secure s32 psci_cpu_off(void)
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{
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+ int cpu;
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+
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+ psci_cpu_off_common();
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+ cpu = psci_get_cpu_id();
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imx_enable_cpu_ca7(cpu, false);
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imx_gpcv2_set_core1_power(false);
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writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
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- return 0;
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+
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+ while (1)
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+ wfi();
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}
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-__secure void imx_system_reset(void)
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+__secure void psci_system_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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@@ -91,9 +102,12 @@ __secure void imx_system_reset(void)
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writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
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writew(WCR_WDE, &wdog->wcr);
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+
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+ while (1)
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+ wfi();
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}
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-__secure void imx_system_off(void)
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+__secure void psci_system_off(void)
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{
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u32 val;
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@@ -103,4 +117,7 @@ __secure void imx_system_off(void)
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val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
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val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
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writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
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+
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+ while (1)
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+ wfi();
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}
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