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@@ -220,7 +220,7 @@ static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
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cs ? STM32_QSPI_CR_FSEL : 0);
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}
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-static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
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+static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
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{
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unsigned int ccr_reg = 0;
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u8 imode, admode, dmode;
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@@ -258,8 +258,11 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
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<< STM32_QSPI_CCR_ADSIZE_SHIFT);
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ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
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}
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+
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+ ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
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ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
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ccr_reg |= cmd;
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+
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return ccr_reg;
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}
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@@ -272,8 +275,7 @@ static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
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| CMD_HAS_DUMMY;
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priv->dummycycles = flash->dummy_byte * 8;
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- ccr_reg = _stm32_qspi_gen_ccr(priv);
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- ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
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+ ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
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_stm32_qspi_wait_for_not_busy(priv);
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@@ -359,9 +361,8 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
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}
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if (flags & SPI_XFER_END) {
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- ccr_reg = _stm32_qspi_gen_ccr(priv);
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- ccr_reg |= STM32_QSPI_CCR_IND_WRITE
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- << STM32_QSPI_CCR_FMODE_SHIFT;
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+ ccr_reg = _stm32_qspi_gen_ccr(priv,
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+ STM32_QSPI_CCR_IND_WRITE);
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_stm32_qspi_wait_for_not_busy(priv);
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@@ -392,9 +393,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
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}
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}
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} else if (din) {
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- ccr_reg = _stm32_qspi_gen_ccr(priv);
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- ccr_reg |= STM32_QSPI_CCR_IND_READ
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- << STM32_QSPI_CCR_FMODE_SHIFT;
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+ ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
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_stm32_qspi_wait_for_not_busy(priv);
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