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@@ -5,6 +5,7 @@
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*/
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#include <common.h>
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+#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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@@ -19,6 +20,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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+#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
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+#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
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+ (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
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+
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#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
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#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
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#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
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@@ -27,6 +32,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
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#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
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+#define GPIO_USB0_PWR_ON 18
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+#define GPIO_USB1_PWR_ON 19
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+
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/* DDR3 static configuration */
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static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
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{0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
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@@ -135,6 +143,8 @@ int board_early_init_f(void)
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int board_init(void)
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{
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+ int ret;
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+
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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@@ -147,6 +157,28 @@ int board_init(void)
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mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
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+ /*
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+ * Set RX Channel Control 0 Register:
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+ * Tests have shown, that setting the LPF_COEF from 0 (1/8)
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+ * to 3 (1/1) results in a more stable USB connection.
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+ */
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+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
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+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
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+ setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
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+
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+ /* Toggle USB power */
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+ ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
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+ if (ret < 0)
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+ return ret;
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+ gpio_direction_output(GPIO_USB0_PWR_ON, 0);
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+ ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
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+ if (ret < 0)
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+ return ret;
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+ gpio_direction_output(GPIO_USB1_PWR_ON, 0);
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+ mdelay(1);
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+ gpio_set_value(GPIO_USB0_PWR_ON, 1);
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+ gpio_set_value(GPIO_USB1_PWR_ON, 1);
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+
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return 0;
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}
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