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@@ -1759,8 +1759,7 @@ typedef struct ccsr_gur {
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/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
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#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
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#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
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-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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- defined(CONFIG_PPC_T4080)
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+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
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#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
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@@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
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#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
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#endif
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-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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- defined(CONFIG_PPC_T4080)
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+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
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#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
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#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
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#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
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