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@@ -21,19 +21,19 @@
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#define SPPCR_IO3FV 0x04
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#define SPPCR_IO2FV 0x02
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#define SPPCR_IO1FV 0x01
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-#define SPBDCR_RXBC0 (1 << 0)
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-#define SPCMD_SCKDEN (1 << 15)
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-#define SPCMD_SLNDEN (1 << 14)
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-#define SPCMD_SPNDEN (1 << 13)
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-#define SPCMD_SSLKP (1 << 7)
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-#define SPCMD_BRDV0 (1 << 2)
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+#define SPBDCR_RXBC0 BIT(0)
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+#define SPCMD_SCKDEN BIT(15)
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+#define SPCMD_SLNDEN BIT(14)
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+#define SPCMD_SPNDEN BIT(13)
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+#define SPCMD_SSLKP BIT(7)
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+#define SPCMD_BRDV0 BIT(2)
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#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
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SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
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SPCMD_BRDV0
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-#define SPBFCR_TXRST (1 << 7)
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-#define SPBFCR_RXRST (1 << 6)
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+#define SPBFCR_TXRST BIT(7)
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+#define SPBFCR_RXRST BIT(6)
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/* SH QSPI register set */
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struct sh_qspi_regs {
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