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@@ -261,8 +261,14 @@ static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
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}
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}
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+u32 __weak imx_get_i2cclk(u32 i2c_num)
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+{
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+ return 0;
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+}
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+
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static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
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static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
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{
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{
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+ struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
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struct imx_lpi2c_reg *regs;
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struct imx_lpi2c_reg *regs;
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u32 val;
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u32 val;
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u32 preescale = 0, best_pre = 0, clkhi = 0;
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u32 preescale = 0, best_pre = 0, clkhi = 0;
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@@ -273,9 +279,18 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
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int i;
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int i;
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regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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regs = (struct imx_lpi2c_reg *)devfdt_get_addr(bus);
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- clock_rate = imx_get_i2cclk(bus->seq);
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- if (!clock_rate)
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- return -EPERM;
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+
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+ if (IS_ENABLED(CONFIG_CLK)) {
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+ clock_rate = clk_get_rate(&i2c_bus->per_clk);
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+ if (clock_rate <= 0) {
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+ dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
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+ return clock_rate;
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+ }
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+ } else {
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+ clock_rate = imx_get_i2cclk(bus->seq);
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+ if (!clock_rate)
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+ return -EPERM;
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+ }
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mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
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mode = (readl(®s->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
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/* disable master mode */
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/* disable master mode */
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@@ -417,6 +432,11 @@ static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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return bus_i2c_set_bus_speed(bus, speed);
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return bus_i2c_set_bus_speed(bus, speed);
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}
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}
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+__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
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+{
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+ return 0;
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+}
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+
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static int imx_lpi2c_probe(struct udevice *bus)
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static int imx_lpi2c_probe(struct udevice *bus)
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{
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{
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struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
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struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
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@@ -440,10 +460,23 @@ static int imx_lpi2c_probe(struct udevice *bus)
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return ret;
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return ret;
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}
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}
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- /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
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- ret = enable_i2c_clk(1, bus->seq);
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- if (ret < 0)
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- return ret;
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+ if (IS_ENABLED(CONFIG_CLK)) {
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+ ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
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+ if (ret) {
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+ dev_err(bus, "Failed to get per clk\n");
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+ return ret;
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+ }
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+ ret = clk_enable(&i2c_bus->per_clk);
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+ if (ret) {
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+ dev_err(bus, "Failed to enable per clk\n");
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+ return ret;
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+ }
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+ } else {
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+ /* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
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+ ret = enable_i2c_clk(1, bus->seq);
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+ if (ret < 0)
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+ return ret;
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+ }
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ret = bus_i2c_init(bus, 100000);
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ret = bus_i2c_init(bus, 100000);
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if (ret < 0)
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if (ret < 0)
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