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@@ -162,7 +162,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
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* Wake up from sleep if necessary
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* Reset PHY, then delay 300ns
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*/
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+#ifdef CONFIG_MX27
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
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+#endif
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miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
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PHY_BMCR_RESET);
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udelay(1000);
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@@ -363,7 +365,8 @@ static int fec_open(struct eth_device *edev)
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/*
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* Enable FEC-Lite controller
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*/
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- writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
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+ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
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+ &fec->eth->ecntrl);
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miiphy_wait_aneg(edev);
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miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
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@@ -490,7 +493,7 @@ static void fec_halt(struct eth_device *dev)
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/*
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* issue graceful stop command to the FEC transmitter if necessary
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*/
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- writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
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+ writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
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&fec->eth->x_cntrl);
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debug("eth_halt: wait for stop regs\n");
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@@ -498,7 +501,7 @@ static void fec_halt(struct eth_device *dev)
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* wait for graceful stop to register
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*/
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while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
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- ; /* FIXME ensure time */
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+ udelay(1);
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/*
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* Disable SmartDMA tasks
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@@ -510,7 +513,7 @@ static void fec_halt(struct eth_device *dev)
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* Disable the Ethernet Controller
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* Note: this will also reset the BD index counter!
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*/
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- writel(0, &fec->eth->ecntrl);
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+ writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
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fec->rbd_index = 0;
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fec->tbd_index = 0;
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debug("eth_halt: done\n");
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@@ -569,7 +572,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
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* wait until frame is sent .
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*/
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while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
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- /* FIXME: Timeout */
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+ udelay(1);
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}
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debug("fec_send: status 0x%x index %d\n",
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readw(&fec->tbd_base[fec->tbd_index].status),
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@@ -688,7 +691,7 @@ static int fec_probe(bd_t *bd)
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fec->xcv_type = MII100;
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/* Reset chip. */
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- writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
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+ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
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while (readl(&fec->eth->ecntrl) & 1)
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udelay(10);
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