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@@ -0,0 +1,77 @@
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+Rockchip LVDS interface
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+------------------
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+
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+Required properties:
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+- compatible: "rockchip,rk3288-lvds";
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+
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+- reg: physical base address of the controller and length
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+ of memory mapped region.
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+- clocks: must include clock specifiers corresponding to entries in the
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+ clock-names property.
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+- clock-names: must contain "pclk_lvds"
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+
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+- rockchip,grf: phandle to the general register files syscon
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+
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+- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or <LVDS_FORMAT_JEIDA>,
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+ This describes how the color bits are laid out in the
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+ serialized LVDS signal.
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+- rockchip,data-width : should be <18> or <24>;
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+- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
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+ <LVDS_OUTPUT_DUAL>, This describes the output face.
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+
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+- display-timings : described by
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+ doc/devicetree/device-tree-bindings/video/display-timing.txt.
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+
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+Example:
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+ lvds: lvds@ff96c000 {
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+ compatible = "rockchip,rk3288-lvds";
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+ reg = <0xff96c000 0x4000>;
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+ clocks = <&cru PCLK_LVDS_PHY>;
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+ clock-names = "pclk_lvds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&lcdc0_ctl>;
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+ rockchip,grf = <&grf>;
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+ status = "disabled";
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ lvds_in: port@0 {
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+ reg = <0>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ lvds_in_vopb: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&vopb_out_lvds>;
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+ };
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+ lvds_in_vopl: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&vopl_out_lvds>;
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+ };
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+ };
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+ };
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+ };
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+
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+ &lvds {
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+ rockchip,data-mapping = <LVDS_FORMAT_VESA>;
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+ rockchip,data-width = <24>;
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+ rockchip,output = <LVDS_OUTPUT_DUAL>;
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+ rockchip,panel = <&panel>;
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+ status = "okay";
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+
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+ display-timings {
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+ timing@0 {
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+ clock-frequency = <40000000>;
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+ hactive = <1920>;
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+ vactive = <1080>;
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+ hsync-len = <44>;
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+ hfront-porch = <88>;
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+ hback-porch = <148>;
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+ vfront-porch = <4>;
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+ vback-porch = <36>;
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+ vsync-len = <5>;
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+ };
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+ };
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+ };
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