ARM: uniphier: add PLL init code for LD11 SoC

 - Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arch/arm/mach-uniphier/board_init.c

@@ -128,6 +128,7 @@ int board_init(void)
 		sg_set_pinsel(153, 14, 8, 4);	/* XIRQ4    -> XIRQ4 */
 		sg_set_iectrl(153);
 		led_puts("U1");
+		uniphier_ld11_pll_init();
 		uniphier_ld11_clk_init();
 		break;
 #endif

arch/arm/mach-uniphier/clk/Makefile

@@ -11,7 +11,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o dpll-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o dpll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o dpll-ld20.o
 
 else
@@ -23,9 +23,10 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o pll-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o pll-ld20.o
 
 endif
 
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pll-base-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pll-base-ld20.o

arch/arm/mach-uniphier/clk/dpll-ld11.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
+{
+	uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	return 0;
+}

arch/arm/mach-uniphier/clk/pll-ld11.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+void uniphier_ld11_pll_init(void)
+{
+	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */
+	/* do nothing for SPLL */
+	uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);	/* 1500MHz -> 1600MHz */
+	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+	mdelay(1);
+
+	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+	writel(0, SC_CA53_GEARSET);	/* Gear0: CPLL/2 */
+	writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+}

arch/arm/mach-uniphier/init.h

@@ -87,6 +87,7 @@ int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
@@ -105,6 +106,7 @@ int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 void uniphier_sld3_pll_init(void);
 void uniphier_ld4_pll_init(void);
 void uniphier_pro4_pll_init(void);
+void uniphier_ld11_pll_init(void);
 int uniphier_ld20_pll_init(const struct uniphier_board_data *bd);
 
 void uniphier_ld4_clk_init(void);

arch/arm/mach-uniphier/init/init-ld11.c

@@ -31,12 +31,14 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd)
 
 	led_puts("L2");
 
-	led_puts("L3");
-
 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 	preloader_console_init();
 #endif
 
+	led_puts("L3");
+
+	uniphier_ld11_dpll_init(bd);
+
 	led_puts("L4");
 
 	{

arch/arm/mach-uniphier/sc64-regs.h

@@ -13,12 +13,14 @@
 #define SC_BASE_ADDR		0x61840000
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD20: CPU/ARM */
-#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD20: misc */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* LD11/20: CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* LD11/20: misc */
 #define SC_SPLL2CTRL	(SC_BASE_ADDR | 0x1420)	/* LD20: IPP */
-#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD20: Video codec */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* LD11/20: Video codec */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD11 */
 #define SC_VPPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* LD20: VPE etc. */
 #define SC_GPPLLCTRL	(SC_BASE_ADDR | 0x1450)	/* LD20: GPU/Mali */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* LD11: DDR memory */
 #define SC_DPLL0CTRL	(SC_BASE_ADDR | 0x1460)	/* LD20: DDR memory 0 */
 #define SC_DPLL1CTRL	(SC_BASE_ADDR | 0x1470)	/* LD20: DDR memory 1 */
 #define SC_DPLL2CTRL	(SC_BASE_ADDR | 0x1480)	/* LD20: DDR memory 2 */
@@ -61,4 +63,12 @@
 #define   SC_CLKCTRL7_UMC31		(1 << 1)
 #define   SC_CLKCTRL7_UMC30		(1 << 0)
 
+#define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8080)
+#define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8084)
+#define SC_CA72_GEARUPD		(SC_BASE_ADDR | 0x8088)
+#define SC_CA53_GEARST		(SC_BASE_ADDR | 0x8080)
+#define SC_CA53_GEARSET		(SC_BASE_ADDR | 0x8084)
+#define SC_CA53_GEARUPD		(SC_BASE_ADDR | 0x8088)
+#define   SC_CA_GEARUPD			(1 << 0)
+
 #endif /* SC64_REGS_H */