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@@ -12,6 +12,41 @@
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#include <asm/arch/hardware.h>
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#ifdef CONFIG_SPL_BUILD
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+static void mmr_unlock(u32 base, u32 partition)
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+{
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+ /* Translate the base address */
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+ phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
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+
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+ /* Unlock the requested partition if locked using two-step sequence */
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+ writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
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+ writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
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+}
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+
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+static void ctrl_mmr_unlock(void)
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+{
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+ /* Unlock all WKUP_CTRL_MMR0 module registers */
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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+
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+ /* Unlock all MCU_CTRL_MMR0 module registers */
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+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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+
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+ /* Unlock all CTRL_MMR0 module registers */
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+ mmr_unlock(CTRL_MMR0_BASE, 0);
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+ mmr_unlock(CTRL_MMR0_BASE, 1);
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+ mmr_unlock(CTRL_MMR0_BASE, 2);
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+ mmr_unlock(CTRL_MMR0_BASE, 3);
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+ mmr_unlock(CTRL_MMR0_BASE, 6);
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+ mmr_unlock(CTRL_MMR0_BASE, 7);
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+}
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+
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static void store_boot_index_from_rom(void)
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{
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u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL;
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@@ -27,6 +62,9 @@ void board_init_f(ulong dummy)
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*/
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store_boot_index_from_rom();
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+ /* Make all control module registers accessible */
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+ ctrl_mmr_unlock();
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+
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/* Init DM early in-order to invoke system controller */
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spl_early_init();
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