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@@ -61,7 +61,11 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
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void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
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enum dcache_option option)
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{
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+#ifdef CONFIG_ARMV7_LPAE
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+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
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+#else
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u32 *page_table = (u32 *)gd->arch.tlb_addr;
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+#endif
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unsigned long upto, end;
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end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
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