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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
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+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@@ -30,10 +30,10 @@
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_I2C
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-#define CONFIG_CMD_IDE
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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+#define CONFIG_CMD_SATA
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_TFTPPUT
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@@ -67,32 +67,12 @@
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#define CONFIG_SYS_ALT_MEMTEST
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/* SATA support */
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-#ifdef CONFIG_CMD_IDE
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-#define __io
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-#define CONFIG_IDE_PREINIT
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-#define CONFIG_MVSATA_IDE
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-
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-/* Needs byte-swapping for ATA data register */
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-#define CONFIG_IDE_SWAP_IO
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-
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-#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
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-#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
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-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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-
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-/* Each 8-bit ATA register is aligned to a 4-bytes address */
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-#define CONFIG_SYS_ATA_STRIDE 4
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-
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-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
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-#define CONFIG_SYS_IDE_MAXBUS 2
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-#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
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-
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-/* ATA registers base is at SATA controller base */
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-#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
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-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
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-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
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-
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+#define CONFIG_SYS_SATA_MAX_DEVICE 2
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+#define CONFIG_SATA_MV
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+#define CONFIG_LIBATA
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+#define CONFIG_LBA48
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+#define CONFIG_EFI_PARTITION
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#define CONFIG_DOS_PARTITION
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-#endif /* CONFIG_CMD_IDE */
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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