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@@ -7,6 +7,7 @@
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*/
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#include <common.h>
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+#include <dm.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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@@ -20,6 +21,8 @@
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#include "ehci.h"
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+DECLARE_GLOBAL_DATA_PTR;
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+
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#define USB1_ADDR_MASK 0xFFFF0000
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#define HOSTPC1_DEVLC 0x84
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@@ -32,9 +35,11 @@
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#endif
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#endif
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+#ifndef CONFIG_DM_USB
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enum {
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USB_PORTS_MAX = 3, /* Maximum ports we allow */
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};
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+#endif
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/* Parameters we need for USB */
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enum {
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@@ -71,12 +76,15 @@ enum usb_ctlr_type {
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/* Information about a USB port */
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struct fdt_usb {
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+ struct ehci_ctrl ehci;
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struct usb_ctlr *reg; /* address of registers in physical memory */
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unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
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unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
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unsigned enabled:1; /* 1 to enable, 0 to disable */
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unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
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+#ifndef CONFIG_DM_USB
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unsigned initialized:1; /* has this port already been initialized? */
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+#endif
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enum usb_ctlr_type type;
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enum usb_init_type init_type;
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enum dr_mode dr_mode; /* dual role mode */
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@@ -85,8 +93,10 @@ struct fdt_usb {
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struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
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};
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+#ifndef CONFIG_DM_USB
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static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
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static unsigned port_count; /* Number of available ports */
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+#endif
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/*
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* This table has USB timing parameters for each Oscillator frequency we
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@@ -163,6 +173,7 @@ static const u8 utmip_elastic_limit = 16;
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static const u8 utmip_hs_sync_start_delay = 9;
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struct fdt_usb_controller {
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+ /* TODO(sjg@chromium.org): Remove when we only use driver model */
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int compat;
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/* flag to determine whether controller supports hostpc register */
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u32 has_hostpc:1;
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@@ -785,6 +796,7 @@ static const struct ehci_ops tegra_ehci_ops = {
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.powerup_fixup = tegra_ehci_powerup_fixup,
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};
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+#ifndef CONFIG_DM_USB
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/*
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* process_usb_nodes() - Process a list of USB nodes, adding them to our list
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* of USB ports.
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@@ -905,3 +917,74 @@ int ehci_hcd_stop(int index)
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return 0;
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}
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+#endif /* !CONFIG_DM_USB */
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+
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+#ifdef CONFIG_DM_USB
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+static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct fdt_usb *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv);
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+ if (ret)
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+ return ret;
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+
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+ priv->type = dev_get_driver_data(dev);
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+
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+ return 0;
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+}
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+
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+static int ehci_usb_probe(struct udevice *dev)
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+{
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+ struct usb_platdata *plat = dev_get_platdata(dev);
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+ struct fdt_usb *priv = dev_get_priv(dev);
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+ struct ehci_hccr *hccr;
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+ struct ehci_hcor *hcor;
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+ static bool clk_done;
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+ int ret;
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+
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+ ret = usb_common_init(priv, plat->init_type);
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+ if (ret)
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+ return ret;
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+ hccr = (struct ehci_hccr *)&priv->reg->cap_length;
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+ hcor = (struct ehci_hcor *)&priv->reg->usb_cmd;
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+ if (!clk_done) {
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+ config_clock(get_pll_timing(&fdt_usb_controllers[priv->type]));
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+ clk_done = true;
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+ }
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+
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+ return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0,
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+ plat->init_type);
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+}
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+
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+static int ehci_usb_remove(struct udevice *dev)
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+{
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+ int ret;
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+
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+ ret = ehci_deregister(dev);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id ehci_usb_ids[] = {
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+ { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
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+ { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
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+ { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(usb_ehci) = {
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+ .name = "ehci_tegra",
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+ .id = UCLASS_USB,
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+ .of_match = ehci_usb_ids,
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+ .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
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+ .probe = ehci_usb_probe,
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+ .remove = ehci_usb_remove,
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+ .ops = &ehci_usb_ops,
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+ .platdata_auto_alloc_size = sizeof(struct usb_platdata),
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+ .priv_auto_alloc_size = sizeof(struct fdt_usb),
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+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
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+};
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+#endif
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