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@@ -117,11 +117,11 @@ static void ether_post_init (int devnum, int hw_addr)
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sync ();
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#endif
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/* reset emac */
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- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
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+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
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sync ();
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for (i = 0;; i++) {
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- if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
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+ if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
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break;
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if (i >= 1000) {
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printf ("Timeout resetting EMAC\n");
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@@ -144,7 +144,7 @@ static void ether_post_init (int devnum, int hw_addr)
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else
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mode_reg |= EMAC_M1_OBCI_GT100;
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- out32 (EMAC_M1 + hw_addr, mode_reg);
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+ out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
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#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
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@@ -212,40 +212,40 @@ static void ether_post_init (int devnum, int hw_addr)
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/* set internal loopback mode */
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#ifdef CFG_POST_ETHER_EXT_LOOPBACK
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- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
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- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
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- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
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- in32 (EMAC_M1));
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+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
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+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
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+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
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+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
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#else
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- out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
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- EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
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- EMAC_M1_MF_100MBPS | EMAC_M1_IST |
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- in32 (EMAC_M1));
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+ out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
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+ EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
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+ EMAC_M1_MF_100MBPS | EMAC_M1_IST |
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+ in_be32 ((void*)(EMAC_M1 + hw_addr)));
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#endif
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/* set transmit enable & receive enable */
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- out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
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+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
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/* enable broadcast address */
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- out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
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+ out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
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/* set transmit request threshold register */
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- out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
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+ out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
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/* set receive low/high water mark register */
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#if defined(CONFIG_440)
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/* 440s has a 64 byte burst length */
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- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
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+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
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#else
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/* 405s have a 16 byte burst length */
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- out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
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+ out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
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#endif /* defined(CONFIG_440) */
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- out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
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+ out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
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/* Set fifo limit entry in tx mode 0 */
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- out32 (EMAC_TXM0 + hw_addr, 0x00000003);
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+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
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/* Frame gap set */
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- out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
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+ out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
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sync ();
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}
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@@ -272,7 +272,7 @@ static void ether_post_halt (int devnum, int hw_addr)
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udelay (1000);
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}
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/* emac reset */
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- out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
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+ out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* remove clocks for EMAC internal loopback */
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@@ -302,7 +302,7 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
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flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
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sync ();
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- out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
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+ out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
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sync ();
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}
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