Merge branch 'master' of git://git.denx.de/u-boot-socfpga

arch/arm/dts/socfpga_cyclone5_mcvevk.dts

@@ -7,7 +7,7 @@
 #include "socfpga_cyclone5.dtsi"
 
 / {
-	model = "DENX MCVEVK";
+	model = "Aries MCVEVK";
 	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
 
 	chosen {
@@ -54,5 +54,6 @@
 };
 
 &usb1 {
+	disable-over-current;
 	status = "okay";
 };

arch/arm/dts/socfpga_cyclone5_socdk.dts

@@ -54,10 +54,18 @@
 	rxc-skew-ps = <2000>;
 };
 
+&gpio0 {
+	status = "okay";
+};
+
 &gpio1 {
 	status = "okay";
 };
 
+&gpio2 {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 

arch/arm/mach-socfpga/Kconfig

@@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_GEN5
 	bool
+	select ALTERA_SDRAM
 
 choice
 	prompt "Altera SOCFPGA board select"
@@ -56,8 +57,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_DENX_MCVEVK
-	bool "DENX MCVEVK (Cyclone V)"
+config TARGET_SOCFPGA_ARIES_MCVEVK
+	bool "Aries MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_EBV_SOCRATES
@@ -97,7 +98,7 @@ config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "is1" if TARGET_SOCFPGA_IS1
-	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
@@ -106,7 +107,7 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
-	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -122,7 +123,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "socfpga_is1" if TARGET_SOCFPGA_IS1
-	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500

arch/arm/mach-socfpga/include/mach/boot0.h

@@ -8,21 +8,17 @@
 #define __BOOT0_H
 
 #ifdef CONFIG_SPL_BUILD
-#define ARM_SOC_BOOT0_HOOK						\
-	.balignl 64,0xf33db33f;						\
-									\
-	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */	\
-	.word	0xc01df00d;	/* Version, flags, length */		\
-	.word	0xcafec0d3;	/* Checksum, zero-pad */		\
-	nop;								\
-									\
-	b reset;		/* SoCFPGA jumps here */		\
-	nop;								\
-	nop;								\
+	.balignl 64,0xf33db33f;
+
+	.word	0x1337c0d3;	/* SoCFPGA preloader validation word */
+	.word	0xc01df00d;	/* Version, flags, length */
+	.word	0xcafec0d3;	/* Checksum, zero-pad */
 	nop;
-#else
-#define ARM_SOC_BOOT0_HOOK
-#endif
 
+	b reset;		/* SoCFPGA jumps here */
+	nop;
+	nop;
+	nop;
+#endif
 
 #endif /* __BOOT0_H */

board/denx/mcvevk/MAINTAINERS → board/aries/mcvevk/MAINTAINERS

@@ -1,5 +1,5 @@
-SOCKIT BOARD
-M:	Marek Vasut <marex@denx.de>
+Aries MCVEVK BOARD
+M:	Marek Vasut <marek.vasut@gmail.com>
 S:	Maintained
 F:	include/configs/socfpga_mcvevk.h
 F:	configs/socfpga_mcvevk_defconfig

configs/socfpga_arria5_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2

configs/socfpga_cyclone5_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2

configs/socfpga_de0_nano_soc_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -58,3 +59,5 @@ CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2

configs/socfpga_de1_soc_defconfig

@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y

configs/socfpga_mcvevk_defconfig

@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
+CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_FIT=y

configs/socfpga_sockit_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y

configs/socfpga_socrates_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y

configs/socfpga_sr1500_defconfig

@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_SR1500=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y

doc/README.socfpga

@@ -1,18 +1,149 @@
-
---------------------------------------------
+----------------------------------------
 SOCFPGA Documentation for U-Boot and SPL
---------------------------------------------
+----------------------------------------
 
 This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
 based SOCFPGA. To know more about the hardware itself, please refer to
 www.altera.com.
 
 
---------------------------------------------
 socfpga_dw_mmc
---------------------------------------------
+--------------
+
 Here are macro and detailed configuration required to enable DesignWare SDMMC
 controller support within SOCFPGA
 
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
+
+--------------------------------------------------
+Generating the handoff header files for U-Boot SPL
+--------------------------------------------------
+
+This text is assuming quartus 16.1, but newer versions will probably work just fine too;
+verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
+Updated/working projects should build using either process below.
+
+Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo
+projects must have the IP cores updated as shown below.
+
+Rebuilding your Quartus project
+-------------------------------
+
+Choose one of the follwing methods, either command line or GUI.
+
+Using the comaand line
+~~~~~~~~~~~~~~~~~~~~~~
+
+First run the embedded command shell, using your path to the Quartus install:
+
+  $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh
+
+Then (if necessary) update the IP cores in the project, generate HDL code, and
+build the project:
+
+  $ cd path/to/project/dir
+  $ qsys-generate soc_system.qsys --upgrade-ip-cores
+  $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
+  $ quartus_sh --flow compile <project name>
+
+Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file):
+
+  $ quartus_cpf -c <project_name>.sof soc_system.rbf
+
+
+Generate BSP handoff files
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+You can run the bsp editor GUI below, or run the following command from the
+project directory:
+
+  $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \
+      --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \
+      --settings build/settings.bsp
+
+You should use the bsp "build" directory above (ie, where the settings.bsp file is)
+in the following u-boot command to update the board headers.  Once these headers
+are updated for a given project build, u-boot should be configured for the
+project board (eg, de0-nano-sockit) and then build the normal spl build.
+
+Now you can skip the GUI section.
+
+
+Using the Qsys GUI
+~~~~~~~~~~~~~~~~~~
+
+1. Navigate to your project directory
+2. Run Quartus II
+3. Open Project (Ctrl+J), select <project_name>.qpf
+4. Run QSys [Tools->QSys]
+  4.1 In the Open dialog, select '<project_name>.qsys'
+  4.2 In the Open System dialog, wait until completion and press 'Close'
+  4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
+     4.3.1 In the 'Generation' window, click 'Generate'
+     4.3.2 In the 'Generate' dialog, wait until completion and click 'Close'
+  4.4 In the QSys window, click 'Finish'
+     4.4.1 In the 'Quartus II' pop up window, click 'OK'
+5. Back in Quartus II main window, do the following
+  5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
+  5.2 Use Processing -> Start Compilation (Ctrl+L)
+
+    ... this may take some time, have patience ...
+
+6. Start the embedded command shell as shown in the previous section
+  6.1 Change directory to 'software/spl_bsp'
+  6.2 Prepare BSP by launching the BSP editor from ECS
+       => bsp-editor
+  6.3 In BSP editor
+      6.3.1 Use File -> Open
+      6.3.2 Select 'settings.bsp' file
+      6.3.3 Click Generate
+      6.3.4 Click Exit
+
+
+Post handoff generation
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Now that the handoff files are generated, U-Boot can be used to process
+the handoff files generated by the bsp-editor. For this, please use the
+following script from the u-boot source tree:
+
+  $ ./arch/arm/mach-socfpga/qts-filter.sh \
+        <soc_type> \
+        <input_qts_dir> \
+        <input_bsp_dir> \
+        <output_dir>
+
+Process QTS-generated files into U-Boot compatible ones.
+
+    soc_type      - Type of SoC, either 'cyclone5' or 'arria5'.
+    input_qts_dir - Directory with compiled Quartus project
+                    and containing the Quartus project file (QPF).
+    input_bsp_dir - Directory with generated bsp containing
+                    the settings.bsp file.
+    output_dir    - Directory to store the U-Boot compatible
+                    headers.
+
+This will generate (or update) the following 4 files:
+
+  iocsr_config.h
+  pinmux_config.h
+  pll_config.h
+  sdram_config.h
+
+These files should be copied into "qts" directory in the board directory
+(see output argument of qts-filter.sh command above).
+
+Here is an example for the DE-0 Nano SoC after the above rebuild process:
+
+  $ ll board/terasic/de0-nano-soc/qts/
+  total 36
+  -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h
+  -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h
+  -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
+  -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h
+
+Note: file sizes will differ slightly depending on the selected board.
+
+Now your board is ready for full mainline support including U-Boot SPL.
+The Preloader will not be needed any more.

drivers/Kconfig

@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"

drivers/ddr/Kconfig

@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"

drivers/ddr/altera/Kconfig

@@ -0,0 +1,5 @@
+config ALTERA_SDRAM
+	bool "SoCFPGA DDR SDRAM driver"
+	depends on TARGET_SOCFPGA_GEN5
+	help
+	  Enable DDR SDRAM controller for the SoCFPGA devices.

drivers/ddr/altera/Makefile

@@ -8,4 +8,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
+ifdef CONFIG_ALTERA_SDRAM
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+endif

include/configs/socfpga_arria5_socdk.h

@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"zImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=n\0" \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiload=sf probe && mtdparts default && run ubiload\0" \
-	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
-		"ubifsload ${loadaddr} /boot/${bootimage} && " \
-		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_common.h

@@ -65,17 +65,15 @@
 #define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
 #endif
 
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+
 /*
  * Cache
  */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 
-/*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
 /*
  * EPCS/EPCQx1 Serial Flash Controller
  */
@@ -230,7 +228,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(32 * 1024 * 1024)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 
 /* USB IDs */
@@ -242,13 +240,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * U-Boot environment
  */
 #if !defined(CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_SIZE			(8 * 1024)
 #endif
 
 /* Environment for SDMMC boot */
 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
-#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
+#define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
+#define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
 #endif
 
 /* Environment for QSPI boot */
@@ -305,8 +303,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	2
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#endif
+#else
+#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
 #endif
 #endif
 
@@ -328,4 +330,41 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
+/* Extra Environment */
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+#ifdef CONFIG_CMD_PXE
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_PXE(func) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"bootm_size=0xa000000\0" \
+	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"scriptaddr=0x02100000\0" \
+	"pxefile_addr_r=0x02200000\0" \
+	"ramdisk_addr_r=0x02300000\0" \
+	BOOTENV
+
+#endif
+#endif
+
 #endif	/* __CONFIG_SOCFPGA_COMMON_H__ */

include/configs/socfpga_cyclone5_socdk.h

@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"zImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=n\0" \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiload=sf probe && mtdparts default && run ubiload\0" \
-	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
-		"ubifsload ${loadaddr} /boot/${bootimage} && " \
-		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_de0_nano_soc.h

@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"fitImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_de1_soc.h

@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"fitImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdtaddr}\0" \
-	"bootimage=zImage\0" \
-	"fdtaddr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdtaddr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdtaddr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdtaddr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_mcvevk.h

@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_DENX_MCVEVK_H__
-#define __CONFIG_DENX_MCVEVK_H__
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
 
 #include <asm/arch/base_addr_ac5.h>
 
@@ -37,6 +37,7 @@
 	"netdev=eth0\0"							\
 	"hostname=mcvevk\0"						\
 	"kernel_addr_r=0x10000000\0"					\
+	"dfu_alt_info=mmc raw 0 3867148288\0"				\
 	"update_filename=u-boot-with-spl.sfp\0"				\
 	"update_sd_offset=0x800\0"					\
 	"update_sd="		/* Update the SD firmware partition */	\
@@ -105,4 +106,4 @@
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 
-#endif	/* __CONFIG_DENX_MCVEVK_H__ */
+#endif	/* __CONFIG_ARIES_MCVEVK_H__ */

include/configs/socfpga_sockit.h

@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"fitImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -30,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=n\0" \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiload=sf probe && mtdparts default && run ubiload\0" \
-	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
-		"ubifsload ${loadaddr} /boot/${bootimage} && " \
-		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_socrates.h

@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCrates */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"zImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -30,29 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=n\0" \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiroot=/dev/mtdblock0\0" \
-	"qspirootfstype=jffs2\0" \
-	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-		"bootm ${loadaddr} - ${fdt_addr}\0"
-
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

include/configs/socfpga_sr1500.h

@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
@@ -28,31 +25,6 @@
 #define CONFIG_PHY_MARVELL
 #define PHY_ANEG_TIMEOUT	8000
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=n\0" \
-	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-		"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"bootimage=zImage\0" \
-	"fdt_addr=100\0" \
-	"fdtimage=socfpga.dtb\0" \
-		"fsloadcmd=ext2load\0" \
-	"bootm ${loadaddr} - ${fdt_addr}\0" \
-	"mmcroot=/dev/mmcblk0p2\0" \
-	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-		" root=${mmcroot} rw rootwait;" \
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"mmcload=mmc rescan;" \
-		"load mmc 0:1 ${loadaddr} ${bootimage};" \
-		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-	"qspiload=sf probe && mtdparts default && run ubiload\0" \
-	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-		"bootz ${loadaddr} - ${fdt_addr}\0" \
-	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
-		"ubifsload ${loadaddr} /boot/${bootimage} && " \
-		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* Environment */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 

include/fdtdec.h

@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,        /* SoCFPGA lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,          /* SoCFPGA fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
 
 	COMPAT_COUNT,
 };

lib/fdtdec.c

@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+	COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+	COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)