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@@ -16,13 +16,15 @@ void lowlevel_init(void)
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int arch_cpu_init(void)
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{
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zynq_slcr_unlock();
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- /* remap DDR to zero, FILTERSTART */
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- writel(0, &scu_base->filter_start);
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/* Device config APB, unlock the PCAP */
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writel(0x757BDF0D, &devcfg_base->unlock);
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writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
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+#if (CONFIG_SYS_SDRAM_BASE == 0)
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+ /* remap DDR to zero, FILTERSTART */
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+ writel(0, &scu_base->filter_start);
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+
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/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
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writel(0x1F, &slcr_base->ocm_cfg);
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/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
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@@ -33,6 +35,7 @@ int arch_cpu_init(void)
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writel(0x0, &slcr_base->ddr_urgent_sel);
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/* Urgent write, ports S2/S3 */
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writel(0xC, &slcr_base->ddr_urgent);
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+#endif
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zynq_slcr_lock();
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