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@@ -24,10 +24,17 @@
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#include <asm/arch/hardware.h>
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#include "videomodes.h"
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-#include <asm/arch/da8xx-fb.h>
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+#include "da8xx-fb.h"
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+
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+#if !defined(DA8XX_LCD_CNTL_BASE)
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+#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
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+#endif
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#define DRIVER_NAME "da8xx_lcdc"
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+#define LCD_VERSION_1 1
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+#define LCD_VERSION_2 2
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+
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/* LCD Status Register */
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#define LCD_END_OF_FRAME1 (1 << 9)
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#define LCD_END_OF_FRAME0 (1 << 8)
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@@ -42,9 +49,14 @@
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#define LCD_DMA_BURST_4 0x2
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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-#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
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+#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
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+#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
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+#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
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#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
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+#define LCD_V2_TFT_24BPP_MODE (1 << 25)
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+#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
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+
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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#define LCD_RASTER_MODE 0x01
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@@ -58,12 +70,20 @@
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#define LCD_MONO_8BIT_MODE (1 << 9)
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#define LCD_RASTER_ORDER (1 << 8)
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#define LCD_TFT_MODE (1 << 7)
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-#define LCD_UNDERFLOW_INT_ENA (1 << 6)
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-#define LCD_PL_ENABLE (1 << 4)
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+#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
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+#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
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+#define LCD_V1_PL_INT_ENA (1 << 4)
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+#define LCD_V2_PL_INT_ENA (1 << 6)
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#define LCD_MONOCHROME_MODE (1 << 1)
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#define LCD_RASTER_ENABLE (1 << 0)
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#define LCD_TFT_ALT_ENABLE (1 << 23)
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#define LCD_STN_565_ENABLE (1 << 24)
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+#define LCD_V2_DMA_CLK_EN (1 << 2)
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+#define LCD_V2_LIDD_CLK_EN (1 << 1)
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+#define LCD_V2_CORE_CLK_EN (1 << 0)
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+#define LCD_V2_LPP_B10 26
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+#define LCD_V2_TFT_24BPP_MODE (1 << 25)
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+#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
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/* LCD Raster Timing 2 Register */
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#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
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@@ -74,6 +94,8 @@
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#define LCD_INVERT_LINE_CLOCK (1 << 21)
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#define LCD_INVERT_FRAME_CLOCK (1 << 20)
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+/* Clock registers available only on Version 2 */
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+#define LCD_CLK_MAIN_RESET (1 << 3)
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/* LCD Block */
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struct da8xx_lcd_regs {
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u32 revid;
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@@ -97,6 +119,15 @@ struct da8xx_lcd_regs {
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u32 dma_frm_buf_ceiling_addr_0;
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u32 dma_frm_buf_base_addr_1;
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u32 dma_frm_buf_ceiling_addr_1;
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+ u32 resv1;
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+ u32 raw_stat;
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+ u32 masked_stat;
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+ u32 int_ena_set;
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+ u32 int_ena_clr;
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+ u32 end_of_int_ind;
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+ /* Clock registers available only on Version 2 */
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+ u32 clk_ena;
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+ u32 clk_reset;
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};
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#define LCD_NUM_BUFFERS 1
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@@ -107,6 +138,8 @@ struct da8xx_lcd_regs {
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#define RIGHT_MARGIN 64
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#define UPPER_MARGIN 32
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#define LOWER_MARGIN 32
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+#define WAIT_FOR_FRAME_DONE true
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+#define NO_WAIT_FOR_FRAME_DONE false
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#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
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@@ -119,6 +152,8 @@ static GraphicDevice gpanel;
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static const struct da8xx_panel *lcd_panel;
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static struct fb_info *da8xx_fb_info;
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static int bits_x_pixel;
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+static unsigned int lcd_revision;
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+const struct lcd_ctrl_config *da8xx_lcd_cfg;
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static inline unsigned int lcdc_read(u32 *addr)
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{
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@@ -179,35 +214,24 @@ static struct fb_fix_screeninfo da8xx_fb_fix = {
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.accel = FB_ACCEL_NONE
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};
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-static const struct display_panel disp_panel = {
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- QVGA,
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- 16,
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- 16,
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- COLOR_ACTIVE,
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-};
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-
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-static const struct lcd_ctrl_config lcd_cfg = {
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- &disp_panel,
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- .ac_bias = 255,
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- .ac_bias_intrpt = 0,
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- .dma_burst_sz = 16,
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- .bpp = 16,
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- .fdd = 255,
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- .tft_alt_mode = 0,
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- .stn_565_mode = 0,
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- .mono_8bit_mode = 0,
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- .invert_line_clock = 1,
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- .invert_frm_clock = 1,
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- .sync_edge = 0,
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- .sync_ctrl = 1,
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- .raster_order = 0,
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-};
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-
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/* Enable the Raster Engine of the LCD Controller */
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static inline void lcd_enable_raster(void)
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{
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u32 reg;
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+ /* Put LCDC in reset for several cycles */
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+ if (lcd_revision == LCD_VERSION_2)
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+ lcdc_write(LCD_CLK_MAIN_RESET,
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+ &da8xx_fb_reg_base->clk_reset);
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+
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+ udelay(1000);
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+ /* Bring LCDC out of reset */
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+ if (lcd_revision == LCD_VERSION_2)
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+ lcdc_write(0,
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+ &da8xx_fb_reg_base->clk_reset);
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+
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+ udelay(1000);
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+
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reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
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if (!(reg & LCD_RASTER_ENABLE))
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lcdc_write(reg | LCD_RASTER_ENABLE,
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@@ -215,14 +239,40 @@ static inline void lcd_enable_raster(void)
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}
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/* Disable the Raster Engine of the LCD Controller */
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-static inline void lcd_disable_raster(void)
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+static inline void lcd_disable_raster(bool wait_for_frame_done)
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{
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u32 reg;
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+ u32 loop_cnt = 0;
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+ u32 stat;
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+ u32 i = 0;
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+
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+ if (wait_for_frame_done)
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+ loop_cnt = 5000;
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reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
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if (reg & LCD_RASTER_ENABLE)
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lcdc_write(reg & ~LCD_RASTER_ENABLE,
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&da8xx_fb_reg_base->raster_ctrl);
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+
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+ /* Wait for the current frame to complete */
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+ do {
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+ if (lcd_revision == LCD_VERSION_1)
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+ stat = lcdc_read(&da8xx_fb_reg_base->stat);
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+ else
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+ stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
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+
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+ mdelay(1);
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+ } while (!(stat & 0x01) && (i++ < loop_cnt));
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+
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+ if (lcd_revision == LCD_VERSION_1)
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+ lcdc_write(stat, &da8xx_fb_reg_base->stat);
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+ else
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+ lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
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+
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+ if ((loop_cnt != 0) && (i >= loop_cnt)) {
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+ printf("LCD Controller timed out\n");
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+ return;
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+ }
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}
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static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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@@ -231,6 +281,7 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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u32 end;
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u32 reg_ras;
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u32 reg_dma;
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+ u32 reg_int;
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/* init reg to clear PLM (loading mode) fields */
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reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
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@@ -243,7 +294,15 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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end = par->dma_end;
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reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
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- reg_dma |= LCD_END_OF_FRAME_INT_ENA;
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+ if (lcd_revision == LCD_VERSION_1) {
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+ reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
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+ } else {
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+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
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+ LCD_V2_END_OF_FRAME0_INT_ENA |
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+ LCD_V2_END_OF_FRAME1_INT_ENA |
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+ LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
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+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
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+ }
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#if (LCD_NUM_BUFFERS == 2)
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reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
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@@ -264,7 +323,13 @@ static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
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end = start + par->palette_sz - 1;
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reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
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- reg_ras |= LCD_PL_ENABLE;
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+ if (lcd_revision == LCD_VERSION_1) {
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+ reg_ras |= LCD_V1_PL_INT_ENA;
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+ } else {
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+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
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+ LCD_V2_PL_INT_ENA;
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+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
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+ }
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lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
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lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
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@@ -348,6 +413,7 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
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static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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{
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u32 reg;
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+ u32 reg_int;
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reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
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LCD_MONO_8BIT_MODE |
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@@ -375,7 +441,13 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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}
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/* enable additional interrupts here */
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- reg |= LCD_UNDERFLOW_INT_ENA;
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+ if (lcd_revision == LCD_VERSION_1) {
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+ reg |= LCD_V1_UNDERFLOW_INT_ENA;
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+ } else {
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+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
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+ LCD_V2_UNDERFLOW_INT_ENA;
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+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
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+ }
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lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
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@@ -413,22 +485,53 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
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/* Set the Panel Width */
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/* Pixels per line = (PPL + 1)*16 */
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- /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
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- width &= 0x3f0;
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+ if (lcd_revision == LCD_VERSION_1) {
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+ /*
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+ * 0x3F in bits 4..9 gives max horisontal resolution = 1024
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+ * pixels
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+ */
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+ width &= 0x3f0;
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+ } else {
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+ /*
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+ * 0x7F in bits 4..10 gives max horizontal resolution = 2048
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+ * pixels.
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+ */
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+ width &= 0x7f0;
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+ }
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reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
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reg &= 0xfffffc00;
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- reg |= ((width >> 4) - 1) << 4;
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+ if (lcd_revision == LCD_VERSION_1) {
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+ reg |= ((width >> 4) - 1) << 4;
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+ } else {
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+ width = (width >> 4) - 1;
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+ reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
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+ }
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lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
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/* Set the Panel Height */
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+ /* Set bits 9:0 of Lines Per Pixel */
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reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
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reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
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lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
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+ /* Set bit 10 of Lines Per Pixel */
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+ if (lcd_revision == LCD_VERSION_2) {
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+ reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
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+ reg |= ((height - 1) & 0x400) << 16;
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+ lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
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+ }
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+
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/* Set the Raster Order of the Frame Buffer */
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reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
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if (raster_order)
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reg |= LCD_RASTER_ORDER;
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+
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+ if (bpp == 24)
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+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
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+ else if (bpp == 32)
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+ reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
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+ | LCD_V2_TFT_24BPP_UNPACK);
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+
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lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
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switch (bpp) {
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@@ -436,6 +539,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
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case 2:
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case 4:
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case 16:
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+ case 24:
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+ case 32:
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par->palette_sz = 16 * 2;
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break;
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@@ -490,6 +595,23 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
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par->pseudo_palette[regno] = red | green | blue;
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+ if (palette[0] != 0x4000) {
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+ update_hw = 1;
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+ palette[0] = 0x4000;
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+ }
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+ } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
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+ ((info->var.bits_per_pixel == 24) && regno < 24)) {
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+ red >>= (24 - info->var.red.length);
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+ red <<= info->var.red.offset;
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+
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+ green >>= (24 - info->var.green.length);
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+ green <<= info->var.green.offset;
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+
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+ blue >>= (24 - info->var.blue.length);
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+ blue <<= info->var.blue.offset;
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+
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+ par->pseudo_palette[regno] = red | green | blue;
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+
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if (palette[0] != 0x4000) {
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update_hw = 1;
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palette[0] = 0x4000;
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@@ -506,11 +628,18 @@ static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
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static void lcd_reset(struct da8xx_fb_par *par)
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{
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/* Disable the Raster if previously Enabled */
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- lcd_disable_raster();
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+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
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/* DMA has to be disabled */
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lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
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lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
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+
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+ if (lcd_revision == LCD_VERSION_2) {
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+ lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
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+ /* Write 1 to reset */
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+ lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
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+ lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
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+ }
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}
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static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
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@@ -521,12 +650,17 @@ static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
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lcd_clk = clk_get(2);
|
|
|
|
|
|
div = lcd_clk / par->pxl_clk;
|
|
|
- debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
|
|
|
- lcd_clk, div, par->pxl_clk);
|
|
|
+ debug("LCD Clock: %d Divider: %d PixClk: %d\n",
|
|
|
+ lcd_clk, div, par->pxl_clk);
|
|
|
|
|
|
/* Configure the LCD clock divisor. */
|
|
|
lcdc_write(LCD_CLK_DIVISOR(div) |
|
|
|
(LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
|
|
|
+
|
|
|
+ if (lcd_revision == LCD_VERSION_2)
|
|
|
+ lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
|
|
|
+ LCD_V2_CORE_CLK_EN,
|
|
|
+ &da8xx_fb_reg_base->clk_ena);
|
|
|
}
|
|
|
|
|
|
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
|
|
@@ -566,7 +700,8 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
|
|
|
- if (QVGA != cfg->p_disp_panel->panel_type)
|
|
|
+ if ((QVGA != cfg->p_disp_panel->panel_type) &&
|
|
|
+ (WVGA != cfg->p_disp_panel->panel_type))
|
|
|
return -EINVAL;
|
|
|
|
|
|
if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
|
|
@@ -602,7 +737,7 @@ static void lcdc_dma_start(void)
|
|
|
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
|
|
|
}
|
|
|
|
|
|
-static u32 lcdc_irq_handler(void)
|
|
|
+static u32 lcdc_irq_handler_rev01(void)
|
|
|
{
|
|
|
struct da8xx_fb_par *par = da8xx_fb_info->par;
|
|
|
u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
|
|
@@ -610,7 +745,7 @@ static u32 lcdc_irq_handler(void)
|
|
|
|
|
|
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
|
|
|
debug("LCD_SYNC_LOST\n");
|
|
|
- lcd_disable_raster();
|
|
|
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
|
|
|
lcdc_write(stat, &da8xx_fb_reg_base->stat);
|
|
|
lcd_enable_raster();
|
|
|
return LCD_SYNC_LOST;
|
|
@@ -622,13 +757,13 @@ static u32 lcdc_irq_handler(void)
|
|
|
* interrupt via the following write to the status register. If
|
|
|
* this is done after then one gets multiple PL done interrupts.
|
|
|
*/
|
|
|
- lcd_disable_raster();
|
|
|
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
|
|
|
|
|
|
lcdc_write(stat, &da8xx_fb_reg_base->stat);
|
|
|
|
|
|
/* Disable PL completion inerrupt */
|
|
|
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
|
|
|
- reg_ras &= ~LCD_PL_ENABLE;
|
|
|
+ reg_ras &= ~LCD_V1_PL_INT_ENA;
|
|
|
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
|
|
|
|
|
|
/* Setup and start data loading mode */
|
|
@@ -650,6 +785,66 @@ static u32 lcdc_irq_handler(void)
|
|
|
return stat;
|
|
|
}
|
|
|
|
|
|
+static u32 lcdc_irq_handler_rev02(void)
|
|
|
+{
|
|
|
+ struct da8xx_fb_par *par = da8xx_fb_info->par;
|
|
|
+ u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
|
|
|
+ u32 reg_int;
|
|
|
+
|
|
|
+ if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
|
|
|
+ debug("LCD_SYNC_LOST\n");
|
|
|
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
|
|
|
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
|
|
|
+ lcd_enable_raster();
|
|
|
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
|
|
|
+ return LCD_SYNC_LOST;
|
|
|
+ } else if (stat & LCD_PL_LOAD_DONE) {
|
|
|
+ debug("LCD_PL_LOAD_DONE\n");
|
|
|
+ /*
|
|
|
+ * Must disable raster before changing state of any control bit.
|
|
|
+ * And also must be disabled before clearing the PL loading
|
|
|
+ * interrupt via the following write to the status register. If
|
|
|
+ * this is done after then one gets multiple PL done interrupts.
|
|
|
+ */
|
|
|
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
|
|
|
+
|
|
|
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
|
|
|
+
|
|
|
+ /* Disable PL completion inerrupt */
|
|
|
+ reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
|
|
|
+ (LCD_V2_PL_INT_ENA);
|
|
|
+ lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
|
|
|
+
|
|
|
+ /* Setup and start data loading mode */
|
|
|
+ lcd_blit(LOAD_DATA, par);
|
|
|
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
|
|
|
+ return LCD_PL_LOAD_DONE;
|
|
|
+ } else {
|
|
|
+ lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
|
|
|
+
|
|
|
+ if (stat & LCD_END_OF_FRAME0)
|
|
|
+ debug("LCD_END_OF_FRAME0\n");
|
|
|
+
|
|
|
+ lcdc_write(par->dma_start,
|
|
|
+ &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
|
|
|
+ lcdc_write(par->dma_end,
|
|
|
+ &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
|
|
|
+ par->vsync_flag = 1;
|
|
|
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
|
|
|
+ return LCD_END_OF_FRAME0;
|
|
|
+ }
|
|
|
+ lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
|
|
|
+ return stat;
|
|
|
+}
|
|
|
+
|
|
|
+static u32 lcdc_irq_handler(void)
|
|
|
+{
|
|
|
+ if (lcd_revision == LCD_VERSION_1)
|
|
|
+ return lcdc_irq_handler_rev01();
|
|
|
+ else
|
|
|
+ return lcdc_irq_handler_rev02();
|
|
|
+}
|
|
|
+
|
|
|
static u32 wait_for_event(u32 event)
|
|
|
{
|
|
|
u32 timeout = 50000;
|
|
@@ -673,6 +868,7 @@ void *video_hw_init(void)
|
|
|
{
|
|
|
struct da8xx_fb_par *par;
|
|
|
u32 size;
|
|
|
+ u32 rev;
|
|
|
char *p;
|
|
|
|
|
|
if (!lcd_panel) {
|
|
@@ -685,6 +881,10 @@ void *video_hw_init(void)
|
|
|
gpanel.plnSizeY = lcd_panel->height;
|
|
|
|
|
|
switch (bits_x_pixel) {
|
|
|
+ case 32:
|
|
|
+ gpanel.gdfBytesPP = 4;
|
|
|
+ gpanel.gdfIndex = GDF_32BIT_X888RGB;
|
|
|
+ break;
|
|
|
case 24:
|
|
|
gpanel.gdfBytesPP = 4;
|
|
|
gpanel.gdfIndex = GDF_32BIT_X888RGB;
|
|
@@ -699,12 +899,29 @@ void *video_hw_init(void)
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
- da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
|
|
|
+ da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
|
|
|
+
|
|
|
+ /* Determine LCD IP Version */
|
|
|
+ rev = lcdc_read(&da8xx_fb_reg_base->revid);
|
|
|
+ switch (rev) {
|
|
|
+ case 0x4C100102:
|
|
|
+ lcd_revision = LCD_VERSION_1;
|
|
|
+ break;
|
|
|
+ case 0x4F200800:
|
|
|
+ case 0x4F201000:
|
|
|
+ lcd_revision = LCD_VERSION_2;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
|
|
|
+ rev);
|
|
|
+ lcd_revision = LCD_VERSION_1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
- debug("Resolution: %dx%d %x\n",
|
|
|
- gpanel.winSizeX,
|
|
|
- gpanel.winSizeY,
|
|
|
- lcd_cfg.bpp);
|
|
|
+ debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
|
|
|
+ gpanel.winSizeX,
|
|
|
+ gpanel.winSizeY,
|
|
|
+ da8xx_lcd_cfg->bpp);
|
|
|
|
|
|
size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
|
|
|
da8xx_fb_info = malloc(size);
|
|
@@ -722,13 +939,14 @@ void *video_hw_init(void)
|
|
|
par = da8xx_fb_info->par;
|
|
|
par->pxl_clk = lcd_panel->pxl_clk;
|
|
|
|
|
|
- if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
|
|
|
+ if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
|
|
|
printf("lcd_init failed\n");
|
|
|
goto err_release_fb;
|
|
|
}
|
|
|
|
|
|
/* allocate frame buffer */
|
|
|
- par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
|
|
|
+ par->vram_size = lcd_panel->width * lcd_panel->height *
|
|
|
+ da8xx_lcd_cfg->bpp;
|
|
|
par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
|
|
|
|
|
|
par->vram_virt = malloc(par->vram_size);
|
|
@@ -741,12 +959,13 @@ void *video_hw_init(void)
|
|
|
printf("GLCD: malloc for frame buffer failed\n");
|
|
|
goto err_release_fb;
|
|
|
}
|
|
|
+ gd->fb_base = (int)par->vram_virt;
|
|
|
|
|
|
gpanel.frameAdrs = (unsigned int)par->vram_virt;
|
|
|
da8xx_fb_info->screen_base = (char *) par->vram_virt;
|
|
|
da8xx_fb_fix.smem_start = gpanel.frameAdrs;
|
|
|
da8xx_fb_fix.smem_len = par->vram_size;
|
|
|
- da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
|
|
|
+ da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
|
|
|
|
|
|
par->dma_start = par->vram_phys;
|
|
|
par->dma_end = par->dma_start + lcd_panel->height *
|
|
@@ -762,7 +981,7 @@ void *video_hw_init(void)
|
|
|
par->p_palette_base = (unsigned int)par->v_palette_base;
|
|
|
|
|
|
/* Initialize par */
|
|
|
- da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
|
|
|
+ da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
|
|
|
|
|
|
da8xx_fb_var.xres = lcd_panel->width;
|
|
|
da8xx_fb_var.xres_virtual = lcd_panel->width;
|
|
@@ -771,8 +990,8 @@ void *video_hw_init(void)
|
|
|
da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
|
|
|
|
|
|
da8xx_fb_var.grayscale =
|
|
|
- lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
|
|
|
- da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
|
|
|
+ da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
|
|
|
+ da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
|
|
|
|
|
|
da8xx_fb_var.hsync_len = lcd_panel->hsw;
|
|
|
da8xx_fb_var.vsync_len = lcd_panel->vsw;
|
|
@@ -787,8 +1006,11 @@ void *video_hw_init(void)
|
|
|
|
|
|
/* Clear interrupt */
|
|
|
memset((void *)par->vram_virt, 0, par->vram_size);
|
|
|
- lcd_disable_raster();
|
|
|
- lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
|
|
|
+ lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
|
|
|
+ if (lcd_revision == LCD_VERSION_1)
|
|
|
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
|
|
|
+ else
|
|
|
+ lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
|
|
|
debug("Palette at 0x%x size %d\n", par->p_palette_base,
|
|
|
par->palette_sz);
|
|
|
lcdc_dma_start();
|
|
@@ -823,8 +1045,10 @@ void video_set_lut(unsigned int index, /* color number */
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
-void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
|
|
|
+void da8xx_video_init(const struct da8xx_panel *panel,
|
|
|
+ const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
|
|
|
{
|
|
|
lcd_panel = panel;
|
|
|
+ da8xx_lcd_cfg = lcd_cfg;
|
|
|
bits_x_pixel = bits_pixel;
|
|
|
}
|