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@@ -19,8 +19,6 @@
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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-#define VDDPU_MASK (0x1f << 9)
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-
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enum ldo_reg {
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LDO_ARM,
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LDO_SOC,
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@@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable)
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writew(enable, &wdog2->wmcr);
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}
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-static void imx_set_vddpu_power_down(void)
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-{
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- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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- struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
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-
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- u32 reg;
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-
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- /*
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- * Disable the brown out detection since we are going to be
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- * disabling the LDO.
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- */
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- reg = readl(&anatop->ana_misc2);
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- reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
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- writel(reg, &anatop->ana_misc2);
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-
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- /* need to power down xPU in GPC before turning off PU LDO */
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- reg = readl(&gpc->gpu_ctrl);
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- writel(reg | 0x1, &gpc->gpu_ctrl);
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-
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- reg = readl(&gpc->ctrl);
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- writel(reg | 0x1, &gpc->ctrl);
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- while (readl(&gpc->ctrl) & 0x1)
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- ;
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-
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- /* Mask the ANATOP brown out interrupt in the GPC. */
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- reg = readl(&gpc->imr4);
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- reg |= 0x80000000;
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- writel(reg, &gpc->imr4);
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-
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- /* disable VDDPU */
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- writel(VDDPU_MASK, &anatop->reg_core_clr);
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-
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- /* Clear the BO interrupt in the ANATOP. */
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- reg = readl(&anatop->ana_misc1);
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- reg |= 0x80000000;
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- writel(reg, &anatop->ana_misc1);
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-}
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-
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int arch_cpu_init(void)
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{
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init_aips();
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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- imx_set_vddpu_power_down();
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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