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@@ -15,6 +15,7 @@
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#include <usbroothubdes.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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+#include <power/regulator.h>
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#include "dwc2.h"
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@@ -159,6 +160,33 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
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mdelay(100);
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}
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+#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
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+static int dwc_vbus_supply_init(struct udevice *dev)
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+{
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+ struct udevice *vbus_supply;
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+ int ret;
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+
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+ ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
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+ if (ret) {
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+ debug("%s: No vbus supply\n", dev->name);
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+ return 0;
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+ }
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+
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+ ret = regulator_set_enable(vbus_supply, true);
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+ if (ret) {
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+ error("Error enabling vbus supply\n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+#else
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+static int dwc_vbus_supply_init(struct udevice *dev)
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+{
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+ return 0;
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+}
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+#endif
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+
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/*
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* This function initializes the DWC_otg controller registers for
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* host mode.
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@@ -167,10 +195,12 @@ static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
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* request queues. Host channels are reset to ensure that they are ready for
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* performing transfers.
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*
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+ * @param dev USB Device (NULL if driver model is not being used)
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* @param regs Programming view of DWC_otg controller
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*
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*/
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-static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
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+static void dwc_otg_core_host_init(struct udevice *dev,
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+ struct dwc2_core_regs *regs)
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{
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uint32_t nptxfifosize = 0;
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uint32_t ptxfifosize = 0;
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@@ -248,6 +278,9 @@ static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
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writel(hprt0, ®s->hprt0);
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}
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}
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+
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+ if (dev)
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+ dwc_vbus_supply_init(dev);
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}
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/*
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@@ -784,12 +817,19 @@ static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
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(*pid << DWC2_HCTSIZ_PID_OFFSET),
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&hc_regs->hctsiz);
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- if (!in && xfer_len) {
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- memcpy(aligned_buffer, buffer, xfer_len);
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-
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- flush_dcache_range((unsigned long)aligned_buffer,
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- (unsigned long)aligned_buffer +
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- roundup(xfer_len, ARCH_DMA_MINALIGN));
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+ if (xfer_len) {
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+ if (in) {
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+ invalidate_dcache_range(
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+ (uintptr_t)aligned_buffer,
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+ (uintptr_t)aligned_buffer +
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+ roundup(xfer_len, ARCH_DMA_MINALIGN));
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+ } else {
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+ memcpy(aligned_buffer, buffer, xfer_len);
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+ flush_dcache_range(
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+ (uintptr_t)aligned_buffer,
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+ (uintptr_t)aligned_buffer +
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+ roundup(xfer_len, ARCH_DMA_MINALIGN));
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+ }
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}
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writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
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@@ -1048,7 +1088,7 @@ int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
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}
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}
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-static int dwc2_init_common(struct dwc2_priv *priv)
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+static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
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{
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struct dwc2_core_regs *regs = priv->regs;
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uint32_t snpsid;
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@@ -1070,7 +1110,7 @@ static int dwc2_init_common(struct dwc2_priv *priv)
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#endif
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dwc_otg_core_init(priv);
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- dwc_otg_core_host_init(regs);
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+ dwc_otg_core_host_init(dev, regs);
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clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
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DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
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@@ -1143,7 +1183,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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if (board_usb_init(index, USB_INIT_HOST))
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return -1;
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- return dwc2_init_common(priv);
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+ return dwc2_init_common(NULL, priv);
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}
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int usb_lowlevel_stop(int index)
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@@ -1214,7 +1254,7 @@ static int dwc2_usb_probe(struct udevice *dev)
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bus_priv->desc_before_addr = true;
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- return dwc2_init_common(priv);
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+ return dwc2_init_common(dev, priv);
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}
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static int dwc2_usb_remove(struct udevice *dev)
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