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@@ -121,7 +121,9 @@
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#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
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-#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
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+#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
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+ typeof(_PTE) (PTE) = (_PTE); \
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+ typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
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((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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@@ -151,27 +153,31 @@
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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-#define write_csr(reg, val) ({ \
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+#define write_csr(reg, _val) ({ \
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+typeof(_val) (val) = (_val); \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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-#define swap_csr(reg, val) ({ unsigned long __tmp; \
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+#define swap_csr(reg, _val) ({ unsigned long __tmp; \
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+typeof(_val) (val) = (_val); \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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else \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; })
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-#define set_csr(reg, bit) ({ unsigned long __tmp; \
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+#define set_csr(reg, _bit) ({ unsigned long __tmp; \
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+typeof(_bit) (bit) = (_bit); \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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-#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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+#define clear_csr(reg, _bit) ({ unsigned long __tmp; \
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+typeof(_bit) (bit) = (_bit); \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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