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@@ -146,12 +146,26 @@
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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+/* I2C */
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+#define CONFIG_SYS_I2C
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+#define CONFIG_SYS_I2C_RCAR
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+#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
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+#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
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+#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
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+#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
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+#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
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+#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
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+#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
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+#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
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+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
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+
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/* Board Clock */
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#define CONFIG_BASE_CLK_FREQ 20000000u
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
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#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
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#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
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+#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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