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@@ -183,33 +183,17 @@ struct zynq_gem_priv {
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struct mii_dev *bus;
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};
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-static inline int mdio_wait(struct zynq_gem_regs *regs)
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-{
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- u32 timeout = 20000;
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-
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- /* Wait till MDIO interface is ready to accept a new transaction. */
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- while (--timeout) {
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- if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
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- break;
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- WATCHDOG_RESET();
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- }
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-
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- if (!timeout) {
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- printf("%s: Timeout\n", __func__);
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- return 1;
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- }
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-
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- return 0;
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-}
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-
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static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
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u32 op, u16 *data)
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{
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u32 mgtcr;
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struct zynq_gem_regs *regs = priv->iobase;
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+ int err;
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- if (mdio_wait(regs))
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- return 1;
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+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
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+ true, 20000, true);
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+ if (err)
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+ return err;
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/* Construct mgtcr mask for the operation */
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mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
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@@ -219,8 +203,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
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/* Write mgtcr and wait for completion */
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writel(mgtcr, ®s->phymntnc);
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- if (mdio_wait(regs))
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- return 1;
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+ err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
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+ true, 20000, true);
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+ if (err)
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+ return err;
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if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
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*data = readl(®s->phymntnc);
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