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@@ -119,7 +119,7 @@ int last_stage_init(void)
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int slaves;
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unsigned int k;
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unsigned int mux_ch;
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- unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
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+ unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
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u16 fpga_features;
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bool hw_type_cat = pca9698_get_value(0x20, 20);
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bool ch0_rgmii2_present = false;
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@@ -131,7 +131,7 @@ int last_stage_init(void)
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ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
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- /* wait for FPGA done */
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+ /* wait for FPGA done, then reset FPGA */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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@@ -146,6 +146,12 @@ int last_stage_init(void)
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break;
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}
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}
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+
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+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
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+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
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+ udelay(10);
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+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
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+ MCFPGA_RESET_N);
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}
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if (hw_type_cat) {
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