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@@ -84,6 +84,7 @@
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10:
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.set pop
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.endm
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+
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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@@ -319,19 +320,21 @@ l1_init:
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
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#endif
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-
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- /* Enable use of the I-cache by setting Config.K0 */
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sync
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- mfc0 t0, CP0_CONFIG
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- li t1, CONFIG_SYS_MIPS_CACHE_MODE
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-#if __mips_isa_rev >= 2
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- ins t0, t1, 0, 3
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-#else
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- ori t0, t0, CONF_CM_CMASK
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- xori t0, t0, CONF_CM_CMASK
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+
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+ /*
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+ * Enable use of the I-cache by setting Config.K0. The code for this
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+ * must be executed from KSEG1. Jump from KSEG0 to KSEG1 to do this.
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+ * Jump back to KSEG0 after caches are enabled and insert an
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+ * instruction hazard barrier.
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+ */
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+ PTR_LA t0, change_k0_cca
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+ li t1, CPHYSADDR(~0)
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+ and t0, t0, t1
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+ PTR_LI t1, CKSEG1
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or t0, t0, t1
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-#endif
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- mtc0 t0, CP0_CONFIG
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+ li a0, CONFIG_SYS_MIPS_CACHE_MODE
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+ jalr.hb t0
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/*
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* then initialize D-cache.
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@@ -391,16 +394,9 @@ l2_unbypass:
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beqz t0, 2f
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/* Change Config.K0 to a coherent CCA */
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- mfc0 t0, CP0_CONFIG
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- li t1, CONF_CM_CACHABLE_COW
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-#if __mips_isa_rev >= 2
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- ins t0, t1, 0, 3
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-#else
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- ori t0, t0, CONF_CM_CMASK
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- xori t0, t0, CONF_CM_CMASK
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- or t0, t0, t1
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-#endif
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- mtc0 t0, CP0_CONFIG
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+ PTR_LA t0, change_k0_cca
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+ li a0, CONF_CM_CACHABLE_COW
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+ jalr t0
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/*
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* Join the coherent domain such that the caches of this core are kept
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@@ -421,5 +417,19 @@ l2_unbypass:
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return:
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/* Ensure all cache operations complete before returning */
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sync
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- jr ra
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+ jr R_RETURN
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END(mips_cache_reset)
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+
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+LEAF(change_k0_cca)
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+ mfc0 t0, CP0_CONFIG
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+#if __mips_isa_rev >= 2
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+ ins t0, a0, 0, 3
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+#else
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+ xor a0, a0, t0
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+ andi a0, a0, CONF_CM_CMASK
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+ xor a0, a0, t0
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+#endif
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+ mtc0 a0, CP0_CONFIG
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+
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+ jr.hb ra
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+ END(change_k0_cca)
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