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@@ -303,7 +303,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
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#ifdef CONFIG_SYS_FSL_DDR4
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#ifdef CONFIG_SYS_FSL_DDR4
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/* tXP=max(4nCK, 6ns) */
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/* tXP=max(4nCK, 6ns) */
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- int txp = max(mclk_ps * 4, 6000); /* unit=ps */
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+ int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
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trwt_mclk = 2;
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trwt_mclk = 2;
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twrt_mclk = 1;
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twrt_mclk = 1;
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act_pd_exit_mclk = picos_to_mclk(txp);
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act_pd_exit_mclk = picos_to_mclk(txp);
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@@ -312,7 +312,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
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* MRS_CYC = max(tMRD, tMOD)
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* MRS_CYC = max(tMRD, tMOD)
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* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
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* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
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*/
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*/
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- tmrd_mclk = max(24, picos_to_mclk(15000));
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+ tmrd_mclk = max(24U, picos_to_mclk(15000));
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#elif defined(CONFIG_SYS_FSL_DDR3)
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#elif defined(CONFIG_SYS_FSL_DDR3)
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unsigned int data_rate = get_ddr_freq(0);
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unsigned int data_rate = get_ddr_freq(0);
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int txp;
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int txp;
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@@ -325,7 +325,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
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* spec has not the tAXPD, we use
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* spec has not the tAXPD, we use
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* tAXPD=1, need design to confirm.
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* tAXPD=1, need design to confirm.
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*/
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*/
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- txp = max(mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
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+ txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
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tmrd_mclk = 4;
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tmrd_mclk = 4;
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/* set the turnaround time */
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/* set the turnaround time */
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@@ -511,8 +511,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
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#ifdef CONFIG_SYS_FSL_DDR4
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#ifdef CONFIG_SYS_FSL_DDR4
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refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
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refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
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wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
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wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
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- acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4);
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- wrtord_mclk = max(2, picos_to_mclk(2500));
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+ acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
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+ wrtord_mclk = max(2U, picos_to_mclk(2500));
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if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
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if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
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printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
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printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
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else
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else
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@@ -627,14 +627,14 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
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wr_data_delay = popts->write_data_delay;
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wr_data_delay = popts->write_data_delay;
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#ifdef CONFIG_SYS_FSL_DDR4
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#ifdef CONFIG_SYS_FSL_DDR4
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cpo = 0;
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cpo = 0;
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- cke_pls = max(3, picos_to_mclk(5000));
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+ cke_pls = max(3U, picos_to_mclk(5000));
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#elif defined(CONFIG_SYS_FSL_DDR3)
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#elif defined(CONFIG_SYS_FSL_DDR3)
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/*
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/*
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* cke pulse = max(3nCK, 7.5ns) for DDR3-800
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* cke pulse = max(3nCK, 7.5ns) for DDR3-800
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* max(3nCK, 5.625ns) for DDR3-1066, 1333
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* max(3nCK, 5.625ns) for DDR3-1066, 1333
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* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
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* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
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*/
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*/
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- cke_pls = max(3, picos_to_mclk(mclk_ps > 1870 ? 7500 :
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+ cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
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(mclk_ps > 1245 ? 5625 : 5000)));
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(mclk_ps > 1245 ? 5625 : 5000)));
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#else
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#else
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cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
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cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
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@@ -1810,9 +1810,9 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
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unsigned int txpr, tcksre, tcksrx;
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unsigned int txpr, tcksre, tcksrx;
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unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
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unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
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- txpr = max(5, picos_to_mclk(common_dimm->trfc1_ps + 10000));
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- tcksre = max(5, picos_to_mclk(10000));
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- tcksrx = max(5, picos_to_mclk(10000));
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+ txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
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+ tcksre = max(5U, picos_to_mclk(10000));
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+ tcksrx = max(5U, picos_to_mclk(10000));
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par_lat = 0;
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par_lat = 0;
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cs_to_cmd = 0;
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cs_to_cmd = 0;
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@@ -1877,7 +1877,7 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
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}
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}
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acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
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acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
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- wrtord_bg = max(4, picos_to_mclk(7500));
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+ wrtord_bg = max(4U, picos_to_mclk(7500));
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if (popts->otf_burst_chop_en)
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if (popts->otf_burst_chop_en)
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wrtord_bg += 2;
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wrtord_bg += 2;
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