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@@ -20,7 +20,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#define RX_BUFFER_SIZE 0x80
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#define RX_BUFFER_SIZE 0x80
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-#ifdef CONFIG_MX6SX
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+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
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#define TX_BUFFER_SIZE 0x200
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#define TX_BUFFER_SIZE 0x200
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#else
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#else
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#define TX_BUFFER_SIZE 0x40
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#define TX_BUFFER_SIZE 0x40
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@@ -268,7 +269,8 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
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INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
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#endif
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#endif
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-#ifdef CONFIG_MX6SX
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+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
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+ defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D)
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/*
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/*
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* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
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* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
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* So, Use IDATSZ in IPCR to determine the size and here set 0.
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* So, Use IDATSZ in IPCR to determine the size and here set 0.
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@@ -905,6 +907,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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qspi->slave.max_write_size = TX_BUFFER_SIZE;
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qspi->slave.max_write_size = TX_BUFFER_SIZE;
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mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
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mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr);
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+
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+ /* Set endianness to LE for i.mx */
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+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
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+ mcr_val = QSPI_MCR_END_CFD_LE;
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+
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qspi_write32(qspi->priv.flags, ®s->mcr,
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qspi_write32(qspi->priv.flags, ®s->mcr,
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
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(mcr_val & QSPI_MCR_END_CFD_MASK));
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(mcr_val & QSPI_MCR_END_CFD_MASK));
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@@ -1023,6 +1030,11 @@ static int fsl_qspi_probe(struct udevice *bus)
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}
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}
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mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
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mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
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+
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+ /* Set endianness to LE for i.mx */
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+ if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7))
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+ mcr_val = QSPI_MCR_END_CFD_LE;
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+
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qspi_write32(priv->flags, &priv->regs->mcr,
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qspi_write32(priv->flags, &priv->regs->mcr,
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
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QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
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(mcr_val & QSPI_MCR_END_CFD_MASK));
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(mcr_val & QSPI_MCR_END_CFD_MASK));
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@@ -1227,6 +1239,8 @@ static const struct dm_spi_ops fsl_qspi_ops = {
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static const struct udevice_id fsl_qspi_ids[] = {
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static const struct udevice_id fsl_qspi_ids[] = {
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{ .compatible = "fsl,vf610-qspi" },
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{ .compatible = "fsl,vf610-qspi" },
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{ .compatible = "fsl,imx6sx-qspi" },
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{ .compatible = "fsl,imx6sx-qspi" },
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+ { .compatible = "fsl,imx6ul-qspi" },
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+ { .compatible = "fsl,imx7d-qspi" },
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{ }
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{ }
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};
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};
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