ARM: s3c44b0: remove remainders of dead board

Because commit 5dc5f36 removed B2 board support,
arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/*
are not necessary anymore.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Andrea Scian <andrea.scian@dave-tech.it>

README

@@ -144,7 +144,6 @@ Directory Hierarchy:
       /arm1136		Files specific to ARM 1136 CPUs
       /ixp		Files specific to Intel XScale IXP CPUs
       /pxa		Files specific to Intel XScale PXA CPUs
-      /s3c44b0		Files specific to Samsung S3C44B0 CPUs
       /sa1100		Files specific to Intel StrongARM SA1100 CPUs
     /lib		Architecture specific library files
   /avr32		Files generic to AVR32 architecture

arch/arm/cpu/s3c44b0/Makefile

@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cache.o
-COBJS	+= cpu.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

arch/arm/cpu/s3c44b0/cache.c

@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-static void s3c44b0_flush_cache(void)
-{
-	volatile int i;
-	/* flush cycle */
-	for(i=0x10002000;i<0x10004800;i+=16)
-	{
-		*((int *)i)=0x0;
-	}
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	s3c44b0_flush_cache();
-
-	/*
-		Init cache
-		Non-cacheable area (everything outside RAM)
-		0x0000:0000 - 0x0C00:0000
-	 */
-	NCACHBE0 = 0xC0000000;
-	NCACHBE1 = 0x00000000;
-
-	/*
-		Enable chache
-	*/
-	reg = SYSCFG;
-	reg |= 0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = SYSCFG;
-	reg &= ~0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-int icache_status (void)
-{
-	return 0;
-}
-
-void dcache_enable (void)
-{
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	return dcache_status();
-}

arch/arm/cpu/s3c44b0/config.mk

@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)

arch/arm/cpu/s3c44b0/cpu.c

@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-int arch_cpu_init (void)
-{
-	icache_enable();
-
-	return 0;
-}
-
-int cleanup_before_linux (void)
-{
-	/*
-		cache memory should be enabled before calling
-		Linux to make the kernel uncompression faster
-	*/
-	icache_enable();
-
-	disable_interrupts ();
-
-	return 0;
-}
-
-void reset_cpu (ulong addr)
-{
-	/*
-		reset the cpu using watchdog
-	*/
-
-	/* Disable the watchdog.*/
-	WTCON&=~(1<<5);
-
-	/* set the timeout value to a short time... */
-	WTCNT = 0x1;
-
-	/* Enable the watchdog. */
-	WTCON|=1;
-	WTCON|=(1<<5);
-
-	while(1) {
-		/*NOP*/
-	}
-}

arch/arm/cpu/s3c44b0/start.S

@@ -1,228 +0,0 @@
-/*
- * Startup Code for S3C44B0 CPU-core
- *
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- * Jump vector table
- */
-
-
-.globl _start
-_start:	b       reset
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate u-boot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-#endif
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	bx	lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#define INTCON (0x01c00000+0x200000)
-#define INTMSK (0x01c00000+0x20000c)
-#define LOCKTIME (0x01c00000+0x18000c)
-#define PLLCON (0x01c00000+0x180000)
-#define CLKCON (0x01c00000+0x180004)
-#define WTCON (0x01c00000+0x130000)
-cpu_init_crit:
-	/* disable watch dog */
-	ldr	r0, =WTCON
-	ldr	r1, =0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	ldr	r1,=INTMSK
-	ldr	r0, =0x03fffeff
-	str	r0, [r1]
-
-	ldr	r1, =INTCON
-	ldr	r0, =0x05
-	str	r0, [r1]
-
-	/* Set Clock Control Register */
-	ldr	r1, =LOCKTIME
-	ldrb	r0, =800
-	strb	r0, [r1]
-
-	ldr	r1, =PLLCON
-
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-
-	str	r0, [r1]
-
-	ldr	r1,=CLKCON
-	ldr	r0, =0x7ff8
-	str	r0, [r1]
-
-	mov	pc, lr
-
-
-/*************************************************/
-/*	interrupt vectors	*/
-/*************************************************/
-real_vectors:
-	b	reset
-	b	undefined_instruction
-	b	software_interrupt
-	b	prefetch_abort
-	b	data_abort
-	b	not_used
-	b	irq
-	b	fiq
-
-/*************************************************/
-
-undefined_instruction:
-	mov	r6, #3
-	b	reset
-
-software_interrupt:
-	mov	r6, #4
-	b	reset
-
-prefetch_abort:
-	mov	r6, #5
-	b	reset
-
-data_abort:
-	mov	r6, #6
-	b	reset
-
-not_used:
-	/* we *should* never reach this */
-	mov	r6, #7
-	b	reset
-
-irq:
-	mov	r6, #8
-	b	reset
-
-fiq:
-	mov	r6, #9
-	b	reset

arch/arm/cpu/s3c44b0/timer.c

@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (TCNTO1 & 0xffff)
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ NOT supported
-#endif
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	TCFG0 = 0x000000E9;
-	TCFG1 = 0x00000004;
-	TCON = 0x00000900;
-	TCNTB1 = TIMER_LOAD_VAL;
-	TCMPB1 = 0;
-	TCON = 0x00000B00;
-	TCON = 0x00000900;
-
-
-	lastdec = TCNTB1 = TIMER_LOAD_VAL;
-	timestamp = 0;
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 8;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-		/*NOP*/;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 8;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*8);
-	}
-
-	endtime = get_timer(0) + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}

arch/arm/include/asm/arch-s3c44b0/hardware.h

@@ -1,281 +0,0 @@
-/********************************************************/
-/*							*/
-/* Samsung S3C44B0					*/
-/* tpu <tapu@371.net>					*/
-/*							*/
-/********************************************************/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define REGBASE		0x01c00000
-#define REGL(addr)	(*(volatile unsigned int *)(REGBASE+addr))
-#define REGW(addr)	(*(volatile unsigned short *)(REGBASE+addr))
-#define REGB(addr)	(*(volatile unsigned char *)(REGBASE+addr))
-
-
-/*****************************/
-/* CPU Wrapper Registers     */
-/*****************************/
-
-#define SYSCFG		REGL(0x000000)
-#define NCACHBE0	REGL(0x000004)
-#define NCACHBE1	REGL(0x000008)
-#define SBUSCON		REGL(0x040000)
-
-/************************************/
-/* Memory Controller Registers      */
-/************************************/
-
-#define BWSCON		REGL(0x080000)
-#define BANKCON0	REGL(0x080004)
-#define BANKCON1	REGL(0x080008)
-#define BANKCON2	REGL(0x08000c)
-#define BANKCON3	REGL(0x080010)
-#define BANKCON4	REGL(0x080014)
-#define BANKCON5	REGL(0x080018)
-#define BANKCON6	REGL(0x08001c)
-#define BANKCON7	REGL(0x080020)
-#define REFRESH		REGL(0x080024)
-#define BANKSIZE	REGL(0x080028)
-#define MRSRB6		REGL(0x08002c)
-#define MRSRB7		REGL(0x080030)
-
-/*********************/
-/* UART Registers    */
-/*********************/
-
-#define ULCON0		REGL(0x100000)
-#define ULCON1		REGL(0x104000)
-#define UCON0		REGL(0x100004)
-#define UCON1		REGL(0x104004)
-#define UFCON0		REGL(0x100008)
-#define UFCON1		REGL(0x104008)
-#define UMCON0		REGL(0x10000c)
-#define UMCON1		REGL(0x10400c)
-#define UTRSTAT0	REGL(0x100010)
-#define UTRSTAT1	REGL(0x104010)
-#define UERSTAT0	REGL(0x100014)
-#define UERSTAT1	REGL(0x104014)
-#define UFSTAT0		REGL(0x100018)
-#define UFSTAT1		REGL(0x104018)
-#define UMSTAT0		REGL(0x10001c)
-#define UMSTAT1		REGL(0x10401c)
-#define UTXH0		REGB(0x100020)
-#define UTXH1		REGB(0x104020)
-#define URXH0		REGB(0x100024)
-#define URXH1		REGB(0x104024)
-#define UBRDIV0		REGL(0x100028)
-#define UBRDIV1		REGL(0x104028)
-
-/*******************/
-/* SIO Registers   */
-/*******************/
-
-#define SIOCON		REGL(0x114000)
-#define SIODAT		REGL(0x114004)
-#define SBRDR		REGL(0x114008)
-#define ITVCNT		REGL(0x11400c)
-#define DCNTZ		REGL(0x114010)
-
-/********************/
-/* IIS Registers    */
-/********************/
-
-#define IISCON		REGL(0x118000)
-#define IISMOD		REGL(0x118004)
-#define IISPSR		REGL(0x118008)
-#define IISFIFCON	REGL(0x11800c)
-#define IISFIF		REGW(0x118010)
-
-/**************************/
-/* I/O Ports Registers    */
-/**************************/
-
-#define PCONA		REGL(0x120000)
-#define PDATA		REGL(0x120004)
-#define PCONB		REGL(0x120008)
-#define PDATB		REGL(0x12000c)
-#define PCONC		REGL(0x120010)
-#define PDATC		REGL(0x120014)
-#define PUPC		REGL(0x120018)
-#define PCOND		REGL(0x12001c)
-#define PDATD		REGL(0x120020)
-#define PUPD		REGL(0x120024)
-#define PCONE		REGL(0x120028)
-#define PDATE		REGL(0x12002c)
-#define PUPE		REGL(0x120030)
-#define PCONF		REGL(0x120034)
-#define PDATF		REGL(0x120038)
-#define PUPF		REGL(0x12003c)
-#define PCONG		REGL(0x120040)
-#define PDATG		REGL(0x120044)
-#define PUPG		REGL(0x120048)
-#define SPUCR		REGL(0x12004c)
-#define EXTINT		REGL(0x120050)
-#define EXTINTPND	REGL(0x120054)
-
-/*********************************/
-/* WatchDog Timers Registers     */
-/*********************************/
-
-#define WTCON		REGL(0x130000)
-#define WTDAT		REGL(0x130004)
-#define WTCNT		REGL(0x130008)
-
-/*********************************/
-/* A/D Converter Registers       */
-/*********************************/
-
-#define ADCCON		REGL(0x140000)
-#define ADCPSR		REGL(0x140004)
-#define ADCDAT		REGL(0x140008)
-
-/***************************/
-/* PWM Timer Registers     */
-/***************************/
-
-#define TCFG0		REGL(0x150000)
-#define TCFG1		REGL(0x150004)
-#define TCON		REGL(0x150008)
-#define TCNTB0		REGL(0x15000c)
-#define TCMPB0		REGL(0x150010)
-#define TCNTO0		REGL(0x150014)
-#define TCNTB1		REGL(0x150018)
-#define TCMPB1		REGL(0x15001c)
-#define TCNTO1		REGL(0x150020)
-#define TCNTB2		REGL(0x150024)
-#define TCMPB2		REGL(0x150028)
-#define TCNTO2		REGL(0x15002c)
-#define TCNTB3		REGL(0x150030)
-#define TCMPB3		REGL(0x150034)
-#define TCNTO3		REGL(0x150038)
-#define TCNTB4		REGL(0x15003c)
-#define TCMPB4		REGL(0x150040)
-#define TCNTO4		REGL(0x150044)
-#define TCNTB5		REGL(0x150048)
-#define TCNTO5		REGL(0x15004c)
-
-/*********************/
-/* IIC Registers     */
-/*********************/
-
-#define IICCON		REGL(0x160000)
-#define IICSTAT		REGL(0x160004)
-#define IICADD		REGL(0x160008)
-#define IICDS		REGL(0x16000c)
-
-/*********************/
-/* RTC Registers     */
-/*********************/
-
-#define RTCCON		REGB(0x170040)
-#define RTCALM		REGB(0x170050)
-#define ALMSEC		REGB(0x170054)
-#define ALMMIN		REGB(0x170058)
-#define ALMHOUR		REGB(0x17005c)
-#define ALMDAY		REGB(0x170060)
-#define ALMMON		REGB(0x170064)
-#define ALMYEAR		REGB(0x170068)
-#define RTCRST		REGB(0x17006c)
-#define BCDSEC		REGB(0x170070)
-#define BCDMIN		REGB(0x170074)
-#define BCDHOUR		REGB(0x170078)
-#define BCDDAY		REGB(0x17007c)
-#define BCDDATE		REGB(0x170080)
-#define BCDMON		REGB(0x170084)
-#define BCDYEAR		REGB(0x170088)
-#define TICINT		REGB(0x17008c)
-
-/*********************************/
-/* Clock & Power Registers       */
-/*********************************/
-
-#define PLLCON		REGL(0x180000)
-#define CLKCON		REGL(0x180004)
-#define CLKSLOW		REGL(0x180008)
-#define LOCKTIME	REGL(0x18000c)
-
-/**************************************/
-/* Interrupt Controller Registers     */
-/**************************************/
-
-#define INTCON		REGL(0x200000)
-#define INTPND		REGL(0x200004)
-#define INTMOD		REGL(0x200008)
-#define INTMSK		REGL(0x20000c)
-#define I_PSLV		REGL(0x200010)
-#define I_PMST		REGL(0x200014)
-#define I_CSLV		REGL(0x200018)
-#define I_CMST		REGL(0x20001c)
-#define I_ISPR		REGL(0x200020)
-#define I_ISPC		REGL(0x200024)
-#define F_ISPR		REGL(0x200038)
-#define F_ISPC		REGL(0x20003c)
-
-/********************************/
-/* LCD Controller Registers     */
-/********************************/
-
-#define LCDCON1		REGL(0x300000)
-#define LCDCON2		REGL(0x300004)
-#define LCDSADDR1	REGL(0x300008)
-#define LCDSADDR2	REGL(0x30000c)
-#define LCDSADDR3	REGL(0x300010)
-#define REDLUT		REGL(0x300014)
-#define GREENLUT	REGL(0x300018)
-#define BLUELUT		REGL(0x30001c)
-#define DP1_2		REGL(0x300020)
-#define DP4_7		REGL(0x300024)
-#define DP3_5		REGL(0x300028)
-#define DP2_3		REGL(0x30002c)
-#define DP5_7		REGL(0x300030)
-#define DP3_4		REGL(0x300034)
-#define DP4_5		REGL(0x300038)
-#define DP6_7		REGL(0x30003c)
-#define LCDCON3		REGL(0x300040)
-#define DITHMODE	REGL(0x300044)
-
-/*********************/
-/* DMA Registers     */
-/*********************/
-
-#define ZDCON0		REGL(0x280000)
-#define ZDISRC0		REGL(0x280004)
-#define ZDIDES0		REGL(0x280008)
-#define ZDICNT0		REGL(0x28000c)
-#define ZDCSRC0		REGL(0x280010)
-#define ZDCDES0		REGL(0x280014)
-#define ZDCCNT0		REGL(0x280018)
-
-#define ZDCON1		REGL(0x280020)
-#define ZDISRC1		REGL(0x280024)
-#define ZDIDES1		REGL(0x280028)
-#define ZDICNT1		REGL(0x28002c)
-#define ZDCSRC1		REGL(0x280030)
-#define ZDCDES1		REGL(0x280034)
-#define ZDCCNT1		REGL(0x280038)
-
-#define BDCON0		REGL(0x380000)
-#define BDISRC0		REGL(0x380004)
-#define BDIDES0		REGL(0x380008)
-#define BDICNT0		REGL(0x38000c)
-#define BDCSRC0		REGL(0x380010)
-#define BDCDES0		REGL(0x380014)
-#define BDCCNT0		REGL(0x380018)
-
-#define BDCON1		REGL(0x380020)
-#define BDISRC1		REGL(0x380024)
-#define BDIDES1		REGL(0x380028)
-#define BDICNT1		REGL(0x38002c)
-#define BDCSRC1		REGL(0x380030)
-#define BDCDES1		REGL(0x380034)
-#define BDCCNT1		REGL(0x380038)
-
-
-#define CLEAR_PEND_INT(n)       I_ISPC = (1<<(n))
-#define INT_ENABLE(n)		INTMSK &= ~(1<<(n))
-#define INT_DISABLE(n)		INTMSK |= (1<<(n))
-
-#define HARD_RESET_NOW()
-
-#endif /* __ASM_ARCH_HARDWARE_H */