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@@ -353,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void)
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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- if (srds_prtcl_s1) {
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+ switch (srds_prtcl_s1) {
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+ case 38:
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+ /* swap first lane and third lane on slot1 */
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+ vsc3316_fsm1_tx[0][1] = 14;
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+ vsc3316_fsm1_tx[6][1] = 0;
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+ vsc3316_fsm1_rx[1][1] = 2;
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+ vsc3316_fsm1_rx[6][1] = 13;
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+ case 40:
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+ case 46:
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+ case 48:
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+ /* swap first lane and third lane on slot2 */
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+ vsc3316_fsm1_tx[2][1] = 8;
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+ vsc3316_fsm1_tx[4][1] = 6;
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+ vsc3316_fsm1_rx[2][1] = 10;
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+ vsc3316_fsm1_rx[5][1] = 5;
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+ default:
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ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
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if (ret)
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return ret;
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+ break;
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}
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srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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- if (srds_prtcl_s2) {
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+ switch (srds_prtcl_s2) {
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+ case 38:
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+ /* swap first lane and third lane on slot3 */
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+ vsc3316_fsm2_tx[2][1] = 11;
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+ vsc3316_fsm2_tx[5][1] = 4;
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+ vsc3316_fsm2_rx[2][1] = 9;
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+ vsc3316_fsm2_rx[4][1] = 7;
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+ case 40:
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+ case 46:
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+ case 48:
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+ case 50:
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+ case 52:
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+ case 54:
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+ /* swap first lane and third lane on slot4 */
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+ vsc3316_fsm2_tx[6][1] = 3;
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+ vsc3316_fsm2_tx[1][1] = 12;
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+ vsc3316_fsm2_rx[0][1] = 1;
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+ vsc3316_fsm2_rx[6][1] = 15;
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+ default:
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ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
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if (ret)
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return ret;
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+ break;
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}
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return 0;
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