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arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is built

SPI controllers SSP1, 2 and 3 require to enable their respective clocks.
Let's enable them only when the SPI controller driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Quentin Schulz 6 년 전
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2개의 변경된 파일5개의 추가작업 그리고 0개의 파일을 삭제
  1. 3 0
      arch/arm/cpu/arm926ejs/spear/cpu.c
  2. 2 0
      arch/arm/include/asm/arch-spear/spr_misc.h

+ 3 - 0
arch/arm/cpu/arm926ejs/spear/cpu.c

@@ -52,6 +52,9 @@ int arch_cpu_init(void)
 #if defined(CONFIG_SPEAR_GPIO)
 	periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
 #endif
+#if defined(CONFIG_PL022_SPI)
+	periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
+#endif
 
 	writel(periph1_clken, &misc_p->periph1_clken);
 

+ 2 - 0
arch/arm/include/asm/arch-spear/spr_misc.h

@@ -146,11 +146,13 @@ struct misc_regs {
 #define MISC_SMIENB			0x00200000
 #define MISC_GPIO3ENB			0x00040000
 #define MISC_GPT3ENB			0x00010000
+#define MISC_SSP3ENB			0x00004000
 #define MISC_GPIO4ENB			0x00002000
 #define MISC_GPT2ENB			0x00000800
 #define MISC_FSMCENB			0x00000200
 #define MISC_I2CENB			0x00000080
 #define MISC_SSP2ENB			0x00000070
+#define MISC_SSP1ENB			0x00000020
 #define MISC_UART0ENB			0x00000008
 
 /*   PERIPH_CLK_CFG   */