armv8: layerscape: csu: enable ns access to PFE registers

Enable all types of non-secure access to PFE block registers.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

arch/arm/include/asm/arch-fsl-layerscape/ns_access.h

@@ -26,6 +26,7 @@ enum csu_cslx_ind {
 	CSU_CSLX_PCIE3_IO,
 	CSU_CSLX_USB3 = 20,
 	CSU_CSLX_USB2,
+	CSU_CSLX_PFE = 23,
 	CSU_CSLX_SERDES = 32,
 	CSU_CSLX_QDMA,
 	CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
 	 {CSU_CSLX_USB3, CSU_ALL_RW},
 	 {CSU_CSLX_USB2, CSU_ALL_RW},
+	 {CSU_CSLX_PFE, CSU_ALL_RW},
 	 {CSU_CSLX_SERDES, CSU_ALL_RW},
 	 {CSU_CSLX_QDMA, CSU_ALL_RW},
 	 {CSU_CSLX_LPUART2, CSU_ALL_RW},