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@@ -569,11 +569,6 @@ static const struct spi_clkreg spi_clkregs[] = {
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.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
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};
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-static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
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-{
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- return (val >> shift) & ((1 << width) - 1);
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-}
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-
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static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
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{
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const struct spi_clkreg *spiclk = NULL;
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@@ -590,7 +585,8 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
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}
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val = readl(&cru->clksel_con[spiclk->reg]);
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- div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
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+ div = bitfield_extract(val, spiclk->div_shift,
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+ CLK_SPI_PLL_DIV_CON_WIDTH);
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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