|
@@ -34,7 +34,9 @@
|
|
|
#define SUNXI_MS_BASE 0x01c07000
|
|
|
#define SUNXI_TVD_BASE 0x01c08000
|
|
|
#define SUNXI_CSI0_BASE 0x01c09000
|
|
|
+#ifndef CONFIG_MACH_SUNXI_H3_H5
|
|
|
#define SUNXI_TVE0_BASE 0x01c0a000
|
|
|
+#endif
|
|
|
#define SUNXI_EMAC_BASE 0x01c0b000
|
|
|
#define SUNXI_LCD0_BASE 0x01c0C000
|
|
|
#define SUNXI_LCD1_BASE 0x01c0d000
|
|
@@ -161,10 +163,18 @@ defined(CONFIG_MACH_SUN50I)
|
|
|
/* module sram */
|
|
|
#define SUNXI_SRAM_C_BASE 0x01d00000
|
|
|
|
|
|
+#ifndef CONFIG_MACH_SUN8I_H3
|
|
|
#define SUNXI_DE_FE0_BASE 0x01e00000
|
|
|
+#else
|
|
|
+#define SUNXI_TVE0_BASE 0x01e00000
|
|
|
+#endif
|
|
|
#define SUNXI_DE_FE1_BASE 0x01e20000
|
|
|
#define SUNXI_DE_BE0_BASE 0x01e60000
|
|
|
+#ifndef CONFIG_MACH_SUN50I_H5
|
|
|
#define SUNXI_DE_BE1_BASE 0x01e40000
|
|
|
+#else
|
|
|
+#define SUNXI_TVE0_BASE 0x01e40000
|
|
|
+#endif
|
|
|
#define SUNXI_MP_BASE 0x01e80000
|
|
|
#define SUNXI_AVG_BASE 0x01ea0000
|
|
|
|