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@@ -59,8 +59,6 @@ static const u32 CCAT_MODE_RUN = 0x0033DC8F;
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DECLARE_GLOBAL_DATA_PTR;
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-static uint32_t mx53_dram_size[2];
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-
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phys_size_t get_effective_memsize(void)
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{
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/*
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@@ -74,15 +72,13 @@ phys_size_t get_effective_memsize(void)
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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- return mx53_dram_size[0];
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+ return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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}
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int dram_init(void)
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{
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- mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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- mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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-
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- gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
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+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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+ gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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return 0;
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}
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@@ -90,10 +86,10 @@ int dram_init(void)
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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- gd->bd->bi_dram[0].size = mx53_dram_size[0];
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+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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- gd->bd->bi_dram[1].size = mx53_dram_size[1];
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+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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return 0;
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}
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