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@@ -99,14 +99,24 @@
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#if defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_38X)
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/* SAR values for Armada 38x */
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/* SAR values for Armada 38x */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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+
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#define SAR_CPU_FREQ_OFFS 10
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#define SAR_CPU_FREQ_OFFS 10
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 4
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#define SAR_BOOT_DEVICE_OFFS 4
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#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
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#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
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+
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+#define BOOT_DEV_SEL_OFFS 4
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+#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS)
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+
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+#define BOOT_FROM_UART 0x28
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+#define BOOT_FROM_SPI 0x32
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+#define BOOT_FROM_MMC 0x30
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+#define BOOT_FROM_MMC_ALT 0x31
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#else
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#else
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/* SAR values for Armada XP */
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/* SAR values for Armada XP */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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+
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_FFC_FREQ_OFFS 24
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#define SAR_FFC_FREQ_OFFS 24
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@@ -115,6 +125,12 @@
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#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
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#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 5
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#define SAR_BOOT_DEVICE_OFFS 5
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#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
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#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
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+
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+#define BOOT_DEV_SEL_OFFS 5
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+#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
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+
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+#define BOOT_FROM_UART 0x2
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+#define BOOT_FROM_SPI 0x3
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#endif
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#endif
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#endif /* _MVEBU_SOC_H */
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#endif /* _MVEBU_SOC_H */
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