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@@ -0,0 +1,128 @@
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+/*
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+ * Device Tree Source for OMAP3 clock data
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+ *
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+ * Copyright (C) 2013 Texas Instruments, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+&scm_clocks {
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+ emac_ick: emac_ick@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,am35xx-gate-clock";
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+ clocks = <&ipss_ick>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <1>;
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+ };
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+
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+ emac_fck: emac_fck@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,gate-clock";
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+ clocks = <&rmii_ck>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <9>;
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+ };
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+
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+ vpfe_ick: vpfe_ick@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,am35xx-gate-clock";
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+ clocks = <&ipss_ick>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <2>;
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+ };
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+
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+ vpfe_fck: vpfe_fck@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,gate-clock";
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+ clocks = <&pclk_ck>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <10>;
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+ };
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+
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+ hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,am35xx-gate-clock";
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+ clocks = <&ipss_ick>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <0>;
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+ };
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+
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+ hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,gate-clock";
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+ clocks = <&sys_ck>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <8>;
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+ };
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+
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+ hecc_ck: hecc_ck@32c {
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+ #clock-cells = <0>;
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+ compatible = "ti,am35xx-gate-clock";
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+ clocks = <&sys_ck>;
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+ reg = <0x032c>;
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+ ti,bit-shift = <3>;
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+ };
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+};
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+&cm_clocks {
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+ ipss_ick: ipss_ick@a10 {
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+ #clock-cells = <0>;
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+ compatible = "ti,am35xx-interface-clock";
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+ clocks = <&core_l3_ick>;
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+ reg = <0x0a10>;
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+ ti,bit-shift = <4>;
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+ };
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+
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+ rmii_ck: rmii_ck {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <50000000>;
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+ };
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+
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+ pclk_ck: pclk_ck {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <27000000>;
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+ };
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+
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+ uart4_ick_am35xx: uart4_ick_am35xx@a10 {
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+ #clock-cells = <0>;
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+ compatible = "ti,omap3-interface-clock";
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+ clocks = <&core_l4_ick>;
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+ reg = <0x0a10>;
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+ ti,bit-shift = <23>;
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+ };
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+
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+ uart4_fck_am35xx: uart4_fck_am35xx@a00 {
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+ #clock-cells = <0>;
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+ compatible = "ti,wait-gate-clock";
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+ clocks = <&core_48m_fck>;
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+ reg = <0x0a00>;
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+ ti,bit-shift = <23>;
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+ };
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+};
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+
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+&cm_clockdomains {
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+ core_l3_clkdm: core_l3_clkdm {
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+ compatible = "ti,clockdomain";
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+ clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
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+ <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
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+ <&hecc_ck>;
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+ };
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+
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+ core_l4_clkdm: core_l4_clkdm {
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+ compatible = "ti,clockdomain";
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+ clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
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+ <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
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+ <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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+ <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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+ <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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+ <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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+ <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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+ <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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+ <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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+ <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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+ <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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+ <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
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+ };
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+};
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