powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2

It is not necessary for all processor to have serdes block 1 & 2.
They may have only one serdes block.

So, put serdes block 1 & 2 related code under defines

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -13,8 +13,12 @@
 #include <asm/errno.h>
 #include "fsl_corenet2_serdes.h"
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 static u64 serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 static u64 serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 static u64 serdes3_prtcl_map;
 #endif
@@ -78,8 +82,12 @@ int is_serdes_configured(enum srds_prtcl device)
 {
 	u64 ret = 0;
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	ret |= (1ULL << device) & serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	ret |= (1ULL << device) & serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	ret |= (1ULL << device) & serdes3_prtcl_map;
 #endif
@@ -97,14 +105,18 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	int i;
 
 	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	case FSL_SRDS_1:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	case FSL_SRDS_2:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 		break;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	case FSL_SRDS_3:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
@@ -163,14 +175,18 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 void fsl_serdes_init(void)
 {
 
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,

arch/powerpc/include/asm/config_mpc85xx.h

@@ -535,6 +535,8 @@
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
@@ -565,6 +567,8 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7