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arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin 9 년 전
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1개의 변경된 파일3개의 추가작업 그리고 0개의 파일을 삭제
  1. 3 0
      arch/arc/lib/cache.c

+ 3 - 0
arch/arc/lib/cache.c

@@ -209,6 +209,9 @@ void cache_init(void)
 	read_decode_cache_bcr_arcv2();
 
 	if (ioc_exists) {
+		flush_dcache_all();
+		invalidate_dcache_all();
+
 		/* IO coherency base - 0x8z */
 		write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
 		/* IO coherency aperture size - 512Mb: 0x8z-0xAz */