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@@ -126,6 +126,12 @@ MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
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return &theadorable_serdes_cfg[0];
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return &theadorable_serdes_cfg[0];
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}
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}
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+u8 board_sat_r_get(u8 dev_num, u8 reg)
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+{
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+ /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
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+ return 0x01;
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+}
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+
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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/* Configure MPP */
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/* Configure MPP */
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