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@@ -467,7 +467,7 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
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return 0;
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}
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-static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
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+static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg)
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{
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const u32 csbits =
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((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
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@@ -478,8 +478,6 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
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u32 ctrl_cfg = cfg->ctrl_cfg;
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- debug("\nConfiguring CTRLCFG\n");
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-
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/*
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* SDRAM Failure When Accessing Non-Existent Memory
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* Set the addrorder field of the SDRAM control register
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@@ -498,10 +496,10 @@ static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
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ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
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ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
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- writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
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+ return ctrl_cfg;
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}
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-static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
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+static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg)
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{
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/*
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* SDRAM Failure When Accessing Non-Existent Memory
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@@ -513,9 +511,7 @@ static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
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const int rows = get_errata_rows(cfg);
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u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
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- debug("Configuring DRAMADDRW\n");
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- writel(dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB),
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- &sdr_ctrl->dram_addrw);
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+ return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
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}
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/* Function to initialize SDRAM MMR */
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@@ -527,9 +523,13 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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(cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
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+ const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
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+ const u32 dram_addrw = sdr_get_addr_rw(cfg);
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+
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writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
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- set_sdr_ctrlcfg(cfg);
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+ debug("\nConfiguring CTRLCFG\n");
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+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
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debug("Configuring DRAMTIMING1\n");
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writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
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@@ -546,7 +546,8 @@ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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debug("Configuring LOWPWRTIMING\n");
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writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
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- set_sdr_addr_rw(cfg);
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+ debug("Configuring DRAMADDRW\n");
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+ writel(dram_addrw, &sdr_ctrl->dram_addrw);
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debug("Configuring DRAMIFWIDTH\n");
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writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
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